Keyword : decision diagram

Enumerating All Spanning Shortest Path Forests with Distance and Capacity Constraints
Yu NAKAHATA Jun KAWAHARA Takashi HORIYAMA Shoji KASAHARA 
Publication:   
Publication Date: 2018/09/01
Vol. E101-A  No. 9 ; pp. 1363-1374
Type of Manuscript:  Special Section PAPER (Special Section on Discrete Mathematics and Its Applications)
Category: 
Keyword: 
graph algorithm, graph partitioning, decision diagram, frontier-based search, enumeration problem, 
 Summary | Full Text:PDF(1.8MB)
A Packet Classifier Based on Prefetching EVMDD (k) Machines
Hiroki NAKAHARA Tsutomu SASAO Munehiro MATSUURA 
Publication:   IEICE TRANSACTIONS on Information and Systems
Publication Date: 2014/09/01
Vol. E97-D  No. 9 ; pp. 2243-2252
Type of Manuscript:  Special Section PAPER (Special Section on Multiple-Valued Logic and VLSI Computing)
Category: Logic Design
Keyword: 
many core, packet classification, decision diagram, multi-valued logic, 
 Summary | Full Text:PDF(2.1MB)
A New Preprocessing Method for Efficient Construction of Decision Diagrams
S. R. MALATHI P. SAKTHIVEL 
Publication:   IEICE TRANSACTIONS on Fundamentals of Electronics, Communications and Computer Sciences
Publication Date: 2014/02/01
Vol. E97-A  No. 2 ; pp. 624-631
Type of Manuscript:  PAPER
Category: Algorithms and Data Structures
Keyword: 
cubes, decision diagram, PLA format, formal verification, BDD pre-processing, 
 Summary | Full Text:PDF(1.4MB)
Techniques of BDD/ZDD: Brief History and Recent Activity
Shin-ichi MINATO 
Publication:   IEICE TRANSACTIONS on Information and Systems
Publication Date: 2013/07/01
Vol. E96-D  No. 7 ; pp. 1419-1429
Type of Manuscript:  INVITED SURVEY PAPER
Category: 
Keyword: 
BDD, ZDD, decision diagram, discrete structure, algorithm, data structure, 
 Summary | Full Text:PDF(1.2MB)
A Unified Framework for Equivalence Verification of Datapath Oriented Applications
Bijan ALIZADEH Masahiro FUJITA 
Publication:   IEICE TRANSACTIONS on Information and Systems
Publication Date: 2009/05/01
Vol. E92-D  No. 5 ; pp. 985-994
Type of Manuscript:  Special Section PAPER (Special Section on Formal Approach)
Category: Hardware Verification
Keyword: 
equivalence verification, canonical form, RTL model, gate-level implementation, decision diagram, 
 Summary | Full Text:PDF(1MB)
DDMF: An Efficient Decision Diagram Structure for Design Verification of Quantum Circuits under a Practical Restriction
Shigeru YAMASHITA Shin-ichi MINATO D. Michael MILLER 
Publication:   IEICE TRANSACTIONS on Fundamentals of Electronics, Communications and Computer Sciences
Publication Date: 2008/12/01
Vol. E91-A  No. 12 ; pp. 3793-3802
Type of Manuscript:  PAPER
Category: VLSI Design Technology and CAD
Keyword: 
quantum circuit, verification, decision diagram, 
 Summary | Full Text:PDF(483.7KB)
An XQDD-Based Verification Method for Quantum Circuits
Shiou-An WANG Chin-Yung LU I-Ming TSAI Sy-Yen KUO 
Publication:   IEICE TRANSACTIONS on Fundamentals of Electronics, Communications and Computer Sciences
Publication Date: 2008/02/01
Vol. E91-A  No. 2 ; pp. 584-594
Type of Manuscript:  PAPER
Category: VLSI Design Technology and CAD
Keyword: 
quantum computing, quantum circuits, verification, decision diagram, 
 Summary | Full Text:PDF(466.9KB)
Design of Decision Diagrams with Increased Functionality of Nodes through Group Theory
Radomir S. STANKOVI Jaakko ASTOLA 
Publication:   IEICE TRANSACTIONS on Fundamentals of Electronics, Communications and Computer Sciences
Publication Date: 2003/03/01
Vol. E86-A  No. 3 ; pp. 693-703
Type of Manuscript:  PAPER
Category: VLSI Design Technology and CAD
Keyword: 
decision diagram, binary decision diagram (BDD), Fourier transform, multiplier, 
 Summary | Full Text:PDF(930.6KB)