IEICE Trans

Keyword : critical path

A Power Grid Optimization Algorithm by Observing Timing Error Risk by IR Drop Yoshiyuki KAWAKAMI Makoto TERAO Masahiro FUKUI Shuji TSUKIYAMA
Publication: IEICE TRANSACTIONS on Fundamentals of Electronics, Communications and Computer Sciences Publication Date: 2008/12/01 Vol. E91-A No. 12 ; pp. 3423-3430 Type of Manuscript: Special Section PAPER (Special Section on VLSI Design and CAD Algorithms) Category: Physical Level Design Keyword: power grid optimization, timing violation, critical path, process variation, IR drop,
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A VLSI Design of a Pipelining and Area-Efficient Reed-Solomon Decoder Wei-min WANG Du-yan BI Xing-min DU Lin-hua MA
Publication: IEICE TRANSACTIONS on Information and Systems Publication Date: 2007/08/01 Vol. E90-D No. 8 ; pp. 1301-1303 Type of Manuscript: LETTER Category: VLSI Systems Keyword: Reed-Solomon code, modified Euclid algorithm, Chien search and Forney algorithm, critical path,
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Timing-Driven Placement Based on Path Topology Analysis Feng CHENG Junfa MAO Xiaochun LI
Publication: IEICE TRANSACTIONS on Fundamentals of Electronics, Communications and Computer Sciences Publication Date: 2005/08/01 Vol. E88-A No. 8 ; pp. 2227-2230 Type of Manuscript: LETTER Category: VLSI Design Technology and CAD Keyword: timing-driven placement, interconnect, delay, critical path,
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Critical Path Selection for Deep Sub-Micron Delay Test and Timing Validation Jing-Jia LIOU Li-C. WANG Angela KRSTIĆ Kwang-Ting (Tim) CHENG
Publication: IEICE TRANSACTIONS on Fundamentals of Electronics, Communications and Computer Sciences Publication Date: 2003/12/01 Vol. E86-A No. 12 ; pp. 3038-3048 Type of Manuscript: Special Section PAPER (Special Section on VLSI Design and CAD Algorithms) Category: Timing Verification and Test Generation Keyword: delay test, critical path, statistical timing analysis,
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Adaptive Rekeying for Secure Multicast Sandeep KULKARNI Bezawada BRUHADESHWAR
Publication: IEICE TRANSACTIONS on Communications Publication Date: 2003/10/01 Vol. E86-B No. 10 ; pp. 2957-2965 Type of Manuscript: Special Section PAPER (IEICE/IEEE Joint Special Issue on Assurance Systems and Networks) Category: Security Keyword: group communication, secure multicast, critical path, adaptive rekeying,
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A High Throughput Pipelined Architecture for Blind Adaptive Equalizer with Minimum Latency Masashi MIZUNO James OKELLO Hiroshi OCHI
Publication: IEICE TRANSACTIONS on Fundamentals of Electronics, Communications and Computer Sciences Publication Date: 2003/08/01 Vol. E86-A No. 8 ; pp. 2011-2019 Type of Manuscript: Special Section PAPER (Special Section on Digital Signal Processing) Category: Keyword: blind equalizer, CMA, critical path, pipelined architecture,
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PCHECK: A Delay Analysis Tool for High Performance LSI Design Yoshio MIKI
Publication: IEICE TRANSACTIONS on Fundamentals of Electronics, Communications and Computer Sciences Publication Date: 1996/12/25 Vol. E79-A No. 12 ; pp. 2117-2122 Type of Manuscript: Special Section PAPER (Special Section on VLSI Design and CAD Algorithms) Category: Keyword: delay analysis, critical path, device delay, wire delay, PCHECK,
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A Global Router Optimizing Timing and Area for High-Speed Bipolar LSIs Ikuo HARADA Yuichiro TAKEI Hitoshi KITAZAWA
Publication: IEICE TRANSACTIONS on Fundamentals of Electronics, Communications and Computer Sciences Publication Date: 1994/12/25 Vol. E77-A No. 12 ; pp. 2058-2066 Type of Manuscript: Special Section PAPER (Special Section on VLSI Design and CAD Algorithms) Category: Keyword: global routing, timing driven layout, bipolar LSI, delay model, routing graph, critical path,
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