Keyword : critical path analysis


Critical Path Based Microarchitectural Bottleneck Analysis for Out-of-Order Execution
Teruo TANIMOTO Takatsugu ONO Koji INOUE 
Publication:   
Publication Date: 2019/06/01
Vol. E102-A  No. 6 ; pp. 758-766
Type of Manuscript:  Special Section PAPER (Special Section on Circuits and Systems)
Category: 
Keyword: 
critical path analysisOut-of-Order processorCPI stackbottleneck analysis
 Summary | Full Text:PDF(1.6MB)

DEMI: A Delay Minimization Algorithm for Cell-Based Digital VLSI Design
Tae Hoon KIM Young Hwan KIM 
Publication:   IEICE TRANSACTIONS on Fundamentals of Electronics, Communications and Computer Sciences
Publication Date: 1999/03/25
Vol. E82-A  No. 3 ; pp. 504-511
Type of Manuscript:  PAPER
Category: VLSI Design Technology and CAD
Keyword: 
delay minimizationcell-based designcritical path analysis
 Summary | Full Text:PDF(229.9KB)

Efficient Timing Verification of Latch-Synchronized Systems
Sang-Yeol HAN Young Hwan KIM 
Publication:   IEICE TRANSACTIONS on Fundamentals of Electronics, Communications and Computer Sciences
Publication Date: 1997/09/25
Vol. E80-A  No. 9 ; pp. 1676-1683
Type of Manuscript:  PAPER
Category: VLSI Design Technology and CAD
Keyword: 
VLSI designsynchronous elementscritical path analysistiming error
 Summary | Full Text:PDF(622.9KB)