Keyword : critical area


Layout-Aware Fast Bridge/Open Test Generation by 2-Step Pattern Reordering
Masayuki ARAI Shingo INUYAMA Kazuhiko IWASAKI 
Publication:   
Publication Date: 2018/12/01
Vol. E101-A  No. 12 ; pp. 2262-2270
Type of Manuscript:  Special Section PAPER (Special Section on VLSI Design and CAD Algorithms)
Category: 
Keyword: 
weighted fault coveragecritical areacritical area analysisbridge faultopen fault
 Summary | Full Text:PDF

Reordering-Based Test Pattern Reduction Considering Critical Area-Aware Weighted Fault Coverage
Masayuki ARAI Kazuhiko IWASAKI 
Publication:   
Publication Date: 2017/07/01
Vol. E100-A  No. 7 ; pp. 1488-1495
Type of Manuscript:  Special Section PAPER (Special Section on Design Methodologies for System on a Chip)
Category: 
Keyword: 
weighted fault coveragecritical areatest cost reductiontest pattern reductionbridge faultopen fault
 Summary | Full Text:PDF

Yield-Optimal Layout Synthesis of CMOS Logic Cells by Wiring Fault Minimization
Tetsuya IIZUKA Makoto IKEDA Kunihiro ASADA 
Publication:   IEICE TRANSACTIONS on Fundamentals of Electronics, Communications and Computer Sciences
Publication Date: 2005/07/01
Vol. E88-A  No. 7 ; pp. 1957-1963
Type of Manuscript:  PAPER
Category: VLSI Design Technology and CAD
Keyword: 
comprehensive cell layout synthesisCMOS logic cellcritical areadefect sensitivityyield optimization
 Summary | Full Text:PDF