Keyword : coupling capacitance


SAT-Based Test Generation for Open Faults Using Fault Excitation Caused by Effect of Adjacent Lines
Jun YAMASHITA Hiroyuki YOTSUYANAGI Masaki HASHIZUME Kozo KINOSHITA 
Publication:   IEICE TRANSACTIONS on Fundamentals of Electronics, Communications and Computer Sciences
Publication Date: 2013/12/01
Vol. E96-A  No. 12 ; pp. 2561-2567
Type of Manuscript:  Special Section PAPER (Special Section on VLSI Design and CAD Algorithms)
Category: Logic Synthesis, Test and Verification
Keyword: 
open faultsadjacent linestest pattern generationcoupling capacitanceSAT-based ATPG
 Summary | Full Text:PDF

Boosted Bit Line Program Scheme for Low Operating Voltage MLC NAND Flash Memory
Youngsun SONG Ki-Tae PARK Myounggon KANG Yunheub SONG Sungsoo LEE Youngho LIM Kang-Deog SUH 
Publication:   IEICE TRANSACTIONS on Electronics
Publication Date: 2010/03/01
Vol. E93-C  No. 3 ; pp. 423-425
Type of Manuscript:  LETTER
Category: Electronic Circuits
Keyword: 
bit linecoupling capacitanceVpass window marginboosted channel
 Summary | Full Text:PDF

A Study of Delay Time on Bit Lines in Megabit SRAM's
Atsushi KINOSHITA Shuji MURAKAMI Yasumasa NISHIMURA Kenji ANAMI 
Publication:   IEICE TRANSACTIONS on Electronics
Publication Date: 1992/11/25
Vol. E75-C  No. 11 ; pp. 1383-1386
Type of Manuscript:  Special Section PAPER (Special Issue on LSI Memories)
Category: 
Keyword: 
SRAMcoupling capacitancebit-line
 Summary | Full Text:PDF