IEICE Trans

Keyword : computer hardware and design

Test Synthesis from Behavioral Description Based on Data Transfer Analysis Mitsuteru YUKISHITA Kiyoshi OGURI Tsukasa KAWAOKA
Publication: IEICE TRANSACTIONS on Information and Systems Publication Date: 1995/03/25 Vol. E78-D No. 3 ; pp. 248-251 Type of Manuscript: Special Section LETTER (Special Issue on Synthesis and Verification of Hardware Design) Category: Keyword: computer hardware and design, hardware description language, test synthesis, SFL,
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Defect-Tolerant WSI File Memory System Using Address Permutation for Spare Allocation Eiji FUJIWARA Masaharu TANAKA
Publication: IEICE TRANSACTIONS on Information and Systems Publication Date: 1995/02/25 Vol. E78-D No. 2 ; pp. 130-137 Type of Manuscript: PAPER Category: Fault Tolerant Computing Keyword: fault tolerant computing, computer hardware and design, computer systems,
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On a Class of Multiple-Valued Logic Functions with Truncated Sum, Differential Product and Not Operations Yutaka HATA Kazuharu YAMATO
Publication: IEICE TRANSACTIONS on Information and Systems Publication Date: 1994/05/25 Vol. E77-D No. 5 ; pp. 567-573 Type of Manuscript: PAPER Category: Computer Hardware and Design Keyword: computer hardware and design, multiple-valued logic, truncated sum, completeness, number of the logic functions,
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Design of Josephson Ternary Delta-Gate (δ-Gate) Ali Massoud HAIDAR Fu-Qiang LI Mititada MORISUE
Publication: IEICE TRANSACTIONS on Information and Systems Publication Date: 1993/08/25 Vol. E76-D No. 8 ; pp. 853-862 Type of Manuscript: PAPER Category: Computer Hardware and Design Keyword: computer hardware and design, multiple-valued logic system, superconducting device,
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An Implementation of Multiple-Valued Logic and Fuzzy Logic Circuits Using 1.5 V Bi-CMOS Current-Mode Circuit Mamoru SASAKI Kazutaka TANIGUCHI Yutaka OGATA Fumio UENO Takahiro INOUE
Publication: IEICE TRANSACTIONS on Information and Systems Publication Date: 1993/05/25 Vol. E76-D No. 5 ; pp. 571-576 Type of Manuscript: Special Section PAPER (Special Issue on Multiple-Valued Logic) Category: Circuits Keyword: computer hardware and design, multiple-valued logic circuit, fuzzy logic circuit, Bi-CMOS current-mode circuit,
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Output Permutation and the Maximum Number of Implicants Needed to Cover the Multiple-Valued Logic Functions Yutaka HATA Kazuharu YAMATO
Publication: IEICE TRANSACTIONS on Information and Systems Publication Date: 1993/05/25 Vol. E76-D No. 5 ; pp. 555-561 Type of Manuscript: Special Section PAPER (Special Issue on Multiple-Valued Logic) Category: Logic Design Keyword: computer hardware and design, multiple-valued some-of-products expressions, optimal output permutation, logic complexity, upper bounds,
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Circuit Complexity and Approximation Method Akira MARUOKA
Publication: IEICE TRANSACTIONS on Information and Systems Publication Date: 1992/01/25 Vol. E75-D No. 1 ; pp. 5-21 Type of Manuscript: INVITED PAPER (Special Section on Theoretical Foundations of Computing) Category: Keyword: theory of computing, algorithm and computational complexity, computer hardware and design,
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