IEICE Trans

Keyword : computer arithmetic

Low-Latency Low-Cost Architecture for Square and Cube Roots Jihyuck JO In-Cheol PARK
Publication: Publication Date: 2017/09/01 Vol. E100-A No. 9 ; pp. 1951-1955 Type of Manuscript: PAPER Category: Digital Signal Processing Keyword: computer arithmetic, cube roots, square roots, non-iterative root calculation,
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Multiplier-less and Table-less Linear Approximation for Square-Related Functions In-Cheol PARK Tae-Hwan KIM
Publication: IEICE TRANSACTIONS on Information and Systems Publication Date: 2010/11/01 Vol. E93-D No. 11 ; pp. 2979-2988 Type of Manuscript: PAPER Category: Fundamentals of Information Systems Keyword: square, square-root, inverse square, inverse square-root, computer arithmetic, approximation, linear interpolation,
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Efficient MRC-Based Residue to Binary Converters for the New Moduli Sets {2²ⁿ, 2ⁿ -1, 2ⁿ⁺¹ -1} and {2²ⁿ, 2ⁿ -1, 2^n-1 -1} Amir Sabbagh MOLAHOSSEINI Chitra DADKHAH Keivan NAVI Mohammad ESHGHI
Publication: IEICE TRANSACTIONS on Information and Systems Publication Date: 2009/09/01 Vol. E92-D No. 9 ; pp. 1628-1638 Type of Manuscript: PAPER Category: Computer Systems Keyword: residue to binary converter, mixed-radix conversion (MRC), residue number system (RNS), computer arithmetic,
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A Hardware Algorithm for Integer Division Using the SD2 Representation Naofumi TAKAGI Shunsuke KADOWAKI Kazuyoshi TAKAGI
Publication: IEICE TRANSACTIONS on Fundamentals of Electronics, Communications and Computer Sciences Publication Date: 2006/10/01 Vol. E89-A No. 10 ; pp. 2874-2881 Type of Manuscript: PAPER Category: VLSI Design Technology and CAD Keyword: computer arithmetic, division, integer division, hardware algorithm, signed-digit representation, VLSI,
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Hardware Algorithm for Computing Reciprocal of Euclidean Norm of a 3-D Vector Fumio KUMAZAWA Naofumi TAKAGI
Publication: IEICE TRANSACTIONS on Fundamentals of Electronics, Communications and Computer Sciences Publication Date: 2006/06/01 Vol. E89-A No. 6 ; pp. 1799-1806 Type of Manuscript: PAPER Category: VLSI Design Technology and CAD Keyword: computer arithmetic, hardware algorithm, reciprocal of the Euclidean norm, digit-recurrence, computer graphics,
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Digit-Recurrence Algorithm for Computing Reciprocal Square-Root Naofumi TAKAGI Daisuke MATSUOKA Kazuyoshi TAKAGI
Publication: IEICE TRANSACTIONS on Fundamentals of Electronics, Communications and Computer Sciences Publication Date: 2003/01/01 Vol. E86-A No. 1 ; pp. 221-228 Type of Manuscript: PAPER Category: VLSI Design Technology and CAD Keyword: computer arithmetic, reciprocal square-root, hardware algorithm, digit-recurrence, computer graphics,
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Design of the Floating-Point Adder Supporting the Format Conversion and the Rounding Operations with Simultaneous Rounding Scheme Woo-Chan PARK Cheol-Ho JEONG Tack-Don HAN
Publication: IEICE TRANSACTIONS on Information and Systems Publication Date: 2002/08/01 Vol. E85-D No. 8 ; pp. 1341-1345 Type of Manuscript: LETTER Category: Computer System Element Keyword: computer arithmetic, floating-point unit, floating-point adder,
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Design of High-Radix VLSI Dividers without Quotient Selection Tables Takafumi AOKI Kimihiko NAKAZAWA Tatsuo HIGUCHI
Publication: IEICE TRANSACTIONS on Fundamentals of Electronics, Communications and Computer Sciences Publication Date: 2001/11/01 Vol. E84-A No. 11 ; pp. 2623-2631 Type of Manuscript: Special Section PAPER (Special Section on VLSI Design and CAD Algorithms) Category: VLSI Design Keyword: computer arithmetic, SRT division, high-radix division, signed-digit number systems, VLSI,
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A Digit-Recurrence Algorithm for Cube Rooting Naofumi TAKAGI
Publication: IEICE TRANSACTIONS on Fundamentals of Electronics, Communications and Computer Sciences Publication Date: 2001/05/01 Vol. E84-A No. 5 ; pp. 1309-1314 Type of Manuscript: PAPER Category: VLSI Design Technology and CAD Keyword: computer arithmetic, cube rooting, hardware algorithm, digit-recurrence algorithm, VLSI,
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Evolutionary Synthesis of Fast Constant-Coefficient Multipliers Naofumi HOMMA Takafumi AOKI Tatsuo HIGUCHI
Publication: IEICE TRANSACTIONS on Fundamentals of Electronics, Communications and Computer Sciences Publication Date: 2000/09/25 Vol. E83-A No. 9 ; pp. 1767-1777 Type of Manuscript: PAPER Category: Nonlinear Problems Keyword: circuit design, computer arithmetic, arithmetic circuits, evolvable hardware, evolutionary computation,
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Radix-2-4-8 CORDIC for Fast Vector Rotation Takafumi AOKI Ichiro KITAORI Tatsuo HIGUCHI
Publication: IEICE TRANSACTIONS on Fundamentals of Electronics, Communications and Computer Sciences Publication Date: 2000/06/25 Vol. E83-A No. 6 ; pp. 1106-1114 Type of Manuscript: Special Section PAPER (Special Section of Papers Selected from 1999 International Technical Conference on Circuits/Systems, Computers and Communications (ITC-CSCC'99)) Category: Keyword: computer arithmetic, arithmetic circuits, CORDIC, VLSI, digital signal processing,
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Signed-Weight Arithmetic and Its Application to a Field-Programmable Digital Filter Architecture Takafumi AOKI Yoshiki SAWADA Tatsuo HIGUCHI
Publication: IEICE TRANSACTIONS on Electronics Publication Date: 1999/09/25 Vol. E82-C No. 9 ; pp. 1687-1698 Type of Manuscript: Special Section PAPER (Special Issue on Integrated Electronics and New System Paradigms) Category: Configurable Computing and Fault Tolerance Keyword: computer arithmetic, redundant number systems, digital signal processing, FIR filter, FPGAs,
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Evolutionary Design of Arithmetic Circuits Takafumi AOKI Naofumi HOMMA Tatsuo HIGUCHI
Publication: IEICE TRANSACTIONS on Fundamentals of Electronics, Communications and Computer Sciences Publication Date: 1999/05/25 Vol. E82-A No. 5 ; pp. 798-806 Type of Manuscript: Special Section PAPER (Special Section on Discrete Mathematics and Its Applications) Category: Keyword: circuit design, computer arithmetic, arithmetic circuits, evolvable hardware, evolutionary computation,
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Floating-Point Divide Operation without Special Hardware Supports Takashi AMISAKI Umpei NAGASHIMA Kazutoshi TANABE
Publication: IEICE TRANSACTIONS on Fundamentals of Electronics, Communications and Computer Sciences Publication Date: 1999/01/25 Vol. E82-A No. 1 ; pp. 173-177 Type of Manuscript: LETTER Category: Numerical Analysis and Optimization Keyword: computer arithmetic, division, FPU, error analysis, special-purpose,
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A Modular Inversion Hardware Algorithm with a Redundant Binary Representation Naofumi TAKAGI
Publication: IEICE TRANSACTIONS on Information and Systems Publication Date: 1993/08/25 Vol. E76-D No. 8 ; pp. 863-869 Type of Manuscript: PAPER Category: Computer Hardware and Design Keyword: computer arithmetic, computer cryptograph, greatest common divisor (GCD), hardware algorithm, modular arithmetic,
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