Keyword : computer architecture

A Lightweight Method to Evaluate Effect of Approximate Memory with Hardware Performance Monitors
Soramichi AKIYAMA 
Publication:   
Publication Date: 2019/12/01
Vol. E102-D  No. 12 ; pp. 2354-2365
Type of Manuscript:  Special Section PAPER (Special Section on Parallel and Distributed Computing and Networking)
Category: Computer System
Keyword: 
approximate memory, computer architecture, memory systems, 
 Summary | Full Text:PDF
Evaluation of Register Number Abstraction for Enhanced Instruction Register Files
Naoki FUJIEDA Kiyohiro SATO Ryodai IWAMOTO Shuichi ICHIKAWA 
Publication:   
Publication Date: 2018/06/01
Vol. E101-D  No. 6 ; pp. 1521-1531
Type of Manuscript:  PAPER
Category: Computer System
Keyword: 
computer architecture, embedded systems, instruction register files, secure processors, 
 Summary | Full Text:PDF
An Inductive Method to Select Simulation Points
MinSeong CHOI Takashi FUKUDA Masahiro GOSHIMA Shuichi SAKAI 
Publication:   IEICE TRANSACTIONS on Information and Systems
Publication Date: 2016/12/01
Vol. E99-D  No. 12 ; pp. 2891-2900
Type of Manuscript:  Special Section PAPER (Special Section on Parallel and Distributed Computing and Networking)
Category: Architecture
Keyword: 
simulation point, sampling simulation, microarchitecture, processor architecture, simulation, computer architecture, 
 Summary | Full Text:PDF
An IP Synthesizer for Limited-Resource DWT Processor
Lan-Rong DUNG 
Publication:   IEICE TRANSACTIONS on Fundamentals of Electronics, Communications and Computer Sciences
Publication Date: 2004/12/01
Vol. E87-A  No. 12 ; pp. 3047-3056
Type of Manuscript:  Special Section PAPER (Special Section on VLSI Design and CAD Algorithms)
Category: System Level Design
Keyword: 
discrete wavelet transform, VLSI, silicon intelligent property, DSP, computer architecture, 
 Summary | Full Text:PDF
Issue Queue Energy Reduction through Dynamic Voltage Scaling
Vasily G. MOSHNYAGA 
Publication:   IEICE TRANSACTIONS on Electronics
Publication Date: 2002/02/01
Vol. E85-C  No. 2 ; pp. 272-278
Type of Manuscript:  Special Section PAPER (Special Issue on High-Performance and Low-Power Microprocessors)
Category: Low-Power Technologies
Keyword: 
issue queue, computer architecture, low power, voltage scaling, 
 Summary | Full Text:PDF
Fast Precise Interrupt Handling without Associative Searching in Multiple Out-Of-Order Issue Processors
Sang-Joon NAM In-Cheol PARK Chong-Min KYUNG 
Publication:   IEICE TRANSACTIONS on Information and Systems
Publication Date: 1999/03/25
Vol. E82-D  No. 3 ; pp. 645-653
Type of Manuscript:  PAPER
Category: Computer Hardware and Design
Keyword: 
computer architecture, precise interrupt, multiple out-of-order issue processors, 
 Summary | Full Text:PDF
REMARC: Reconfigurable Multimedia Array Coprocessor
Takashi MIYAMORI Kunle OLUKOTUN 
Publication:   IEICE TRANSACTIONS on Information and Systems
Publication Date: 1999/02/25
Vol. E82-D  No. 2 ; pp. 389-397
Type of Manuscript:  PAPER
Category: Computer Hardware and Design
Keyword: 
computer architecture, reconfigurable computer, array processor, multimedia application, 
 Summary | Full Text:PDF
A Supplementary Scheme for Reducing Cache Access Time
Jong-Hong BAE Chong-Min KYUNG 
Publication:   IEICE TRANSACTIONS on Information and Systems
Publication Date: 1996/04/25
Vol. E79-D  No. 4 ; pp. 385-387
Type of Manuscript:  LETTER
Category: Computer Hardware and Design
Keyword: 
computer architecture, cache, penalty cycles, pipeline, 
 Summary | Full Text:PDF
Neural Network Multiprocessors Applied with Dynamically Reconfigurable Pipeline Architecture
Takayuki MORISHITA Iwao TERAMOTO 
Publication:   IEICE TRANSACTIONS on Electronics
Publication Date: 1994/12/25
Vol. E77-C  No. 12 ; pp. 1937-1943
Type of Manuscript:  Special Section PAPER (Special Issue on Multimedia, Analog and Processing LSIs)
Category: Processors
Keyword: 
neural network, digital processor, back-propagation, multiprocessors' configuration, computer architecture, 
 Summary | Full Text:PDF