Keyword : comprehensive cell layout synthesis

Yield-Optimal Layout Synthesis of CMOS Logic Cells by Wiring Fault Minimization
Tetsuya IIZUKA Makoto IKEDA Kunihiro ASADA 
Publication:   IEICE TRANSACTIONS on Fundamentals of Electronics, Communications and Computer Sciences
Publication Date: 2005/07/01
Vol. E88-A  No. 7 ; pp. 1957-1963
Type of Manuscript:  PAPER
Category: VLSI Design Technology and CAD
comprehensive cell layout synthesisCMOS logic cellcritical areadefect sensitivityyield optimization
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