IEICE Trans

Keyword : compiler

An Integrated Framework for Energy Optimization of Embedded Real-Time Applications Hideki TAKASE Gang ZENG Lovic GAUTHIER Hirotaka KAWASHIMA Noritoshi ATSUMI Tomohiro TATEMATSU Yoshitake KOBAYASHI Takenori KOSHIRO Tohru ISHIHARA Hiroyuki TOMIYAMA Hiroaki TAKADA
Publication: IEICE TRANSACTIONS on Fundamentals of Electronics, Communications and Computer Sciences Publication Date: 2014/12/01 Vol. E97-A No. 12 ; pp. 2477-2487 Type of Manuscript: Special Section PAPER (Special Section on VLSI Design and CAD Algorithms) Category: High-Level Synthesis and System-Level Design Keyword: energy optimization, compiler, profiler, real-time operating systems, embedded systems,
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Fine-Grained Run-Tume Power Gating through Co-optimization of Circuit, Architecture, and System Software Design Hiroshi NAKAMURA Weihan WANG Yuya OHTA Kimiyoshi USAMI Hideharu AMANO Masaaki KONDO Mitaro NAMIKI
Publication: IEICE TRANSACTIONS on Electronics Publication Date: 2013/04/01 Vol. E96-C No. 4 ; pp. 404-412 Type of Manuscript: INVITED PAPER (Special Section on Solid-State Circuit Design—Architecture, Circuit, Device and Design Methodology) Category: Keyword: low-power circuit techniques, fine grained power-gating, compiler, system hierarchy cooperation,
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DiSCo: Distributed Scalable Compilation Tool for Heavy Compilation Workload Kyongjin JO Seon Wook KIM Jong-Kook KIM
Publication: IEICE TRANSACTIONS on Information and Systems Publication Date: 2013/03/01 Vol. E96-D No. 3 ; pp. 589-600 Type of Manuscript: PAPER Category: Fundamentals of Information Systems Keyword: distributed compiler, remote linking, compiler,
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Partitioning and Allocation of Scratch-Pad Memory for Energy Minimization of Priority-Based Preemptive Multi-Task Systems Hideki TAKASE Hiroyuki TOMIYAMA Hiroaki TAKADA
Publication: IEICE TRANSACTIONS on Fundamentals of Electronics, Communications and Computer Sciences Publication Date: 2011/10/01 Vol. E94-A No. 10 ; pp. 1954-1964 Type of Manuscript: PAPER Category: VLSI Design Technology and CAD Keyword: scratch-pad memory, energy optimization, compiler, code allocation, multi-task systems,
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A Cycle-Accurate Simulator for a Reconfigurable Multi-Media System Min ZHU Leibo LIU Shouyi YIN Chongyong YIN Shaojun WEI
Publication: IEICE TRANSACTIONS on Information and Systems Publication Date: 2010/12/01 Vol. E93-D No. 12 ; pp. 3202-3210 Type of Manuscript: Special Section PAPER (Special Section on Parallel and Distributed Computing and Networking) Category: Keyword: SimREMUS, simulator, reconfigurable multimedia system, compiler, debugger,
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Heuristic Instruction Scheduling Algorithm Using Available Distance for Partial Forwarding Processor Takuji HIEDA Hiroaki TANAKA Keishi SAKANUSHI Yoshinori TAKEUCHI Masaharu IMAI
Publication: IEICE TRANSACTIONS on Fundamentals of Electronics, Communications and Computer Sciences Publication Date: 2009/12/01 Vol. E92-A No. 12 ; pp. 3258-3267 Type of Manuscript: Special Section PAPER (Special Section on VLSI Design and CAD Algorithms) Category: Embedded, Real-Time and Reconfigurable Systems Keyword: partial forwarding, instruction scheduling, compiler, design space exploration,
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Generation of Pack Instruction Sequence for Media Processors Using Multi-Valued Decision Diagram Hiroaki TANAKA Yoshinori TAKEUCHI Keishi SAKANUSHI Masaharu IMAI Hiroki TAGAWA Yutaka OTA Nobu MATSUMOTO
Publication: IEICE TRANSACTIONS on Fundamentals of Electronics, Communications and Computer Sciences Publication Date: 2007/12/01 Vol. E90-A No. 12 ; pp. 2800-2809 Type of Manuscript: Special Section PAPER (Special Section on VLSI Design and CAD Algorithms) Category: System Level Design Keyword: compiler, SIMD instructions, multi-valued decision diagram,
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Compiler for Architecture with Dynamic Reconfigurable Processing Unit by Use of Automatic Assignment Method of Sub-Programs Based on Their Quantitative Evaluation Takefumi MIYOSHI Nobuhiko SUGINO
Publication: IEICE TRANSACTIONS on Information and Systems Publication Date: 2007/12/01 Vol. E90-D No. 12 ; pp. 1967-1976 Type of Manuscript: Special Section PAPER (Special Section on Reconfigurable Systems) Category: Reconfigurable Device and Design Tools Keyword: dynamic reconfigurable processor, compiler, automatic context generation,
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Loop and Address Code Optimization for Digital Signal Processors Jong-Yeol LEE In-Cheol PARK
Publication: IEICE TRANSACTIONS on Fundamentals of Electronics, Communications and Computer Sciences Publication Date: 2002/06/01 Vol. E85-A No. 6 ; pp. 1408-1415 Type of Manuscript: LETTER Category: Digital Signal Processing Keyword: digital signal processor (DSP), compiler, code optimization,
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Hardware Synthesis from C Programs with Estimation of Bit Length of Variables Osamu OGAWA Kazuyoshi TAKAGI Yasufumi ITOH Shinji KIMURA Katsumasa WATANABE
Publication: IEICE TRANSACTIONS on Fundamentals of Electronics, Communications and Computer Sciences Publication Date: 1999/11/25 Vol. E82-A No. 11 ; pp. 2338-2346 Type of Manuscript: Special Section PAPER (Special Section on VLSI Design and CAD Algorithms) Category: Keyword: high-level synthesis, hardware/software codesign, VHDL, C language, compiler,
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An Analysis for Fast Construction of States in the Bottom-Up Tree Pattern Matching Scheme Kyung-Woo KANG Kwang-Moo CHOE Min-Soo JUNG
Publication: IEICE TRANSACTIONS on Information and Systems Publication Date: 1999/05/25 Vol. E82-D No. 5 ; pp. 973-976 Type of Manuscript: PAPER Category: Sofware System Keyword: compiler, code generator generator, tree grammar, dynamic programming,
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A VLIW Geometry Processor with Software Bypass Mechanism Yasunori KIMURA Akira ASATO Toshihiro OZAWA Hiroshi NAKAYAMA
Publication: IEICE TRANSACTIONS on Electronics Publication Date: 1998/05/25 Vol. E81-C No. 5 ; pp. 669-679 Type of Manuscript: Special Section PAPER (Special Issue on Multimedia, Network, and DRAM LSIs) Category: Keyword: 3D graphics, geometry processing, VLIW, compiler,
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DSP Code Optimization Methods Utilizing Addressing Operations at the Codes without Memory Accesses Nobuhiko SUGINO Hironobu MIYAZAKI Akinori NISHIHARA
Publication: IEICE TRANSACTIONS on Fundamentals of Electronics, Communications and Computer Sciences Publication Date: 1997/12/25 Vol. E80-A No. 12 ; pp. 2562-2571 Type of Manuscript: PAPER Category: Digital Signal Processing Keyword: digital signal processor, compiler, code optimization, memory addressing,
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Peephole Optimizer in Retargetable Compilers^* Tzer-Shyong CHEN Feipei LAI Shu-Lin HWANG Rung-Ji SHANG
Publication: IEICE TRANSACTIONS on Information and Systems Publication Date: 1996/09/25 Vol. E79-D No. 9 ; pp. 1248-1256 Type of Manuscript: PAPER Category: Sofware System Keyword: code generator, compiler, peephole optimizer, retargetable compiler,
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Eliminating Unnecessary Items from the One-Pass Evaluation of Attribute Grammars Yoshimichi WATANABE Takehiro TOKUDA
Publication: IEICE TRANSACTIONS on Information and Systems Publication Date: 1996/04/25 Vol. E79-D No. 4 ; pp. 312-320 Type of Manuscript: PAPER Category: Software Theory Keyword: attribute grammar, compiler, formal language,
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