Keyword : compaction


An Iterative Improvement Method for Generating Compact Tests for IDDQ Testing of Bridging Faults
Tsuyoshi SHINOGI Terumine HAYASHI 
Publication:   IEICE TRANSACTIONS on Information and Systems
Publication Date: 1998/07/25
Vol. E81-D  No. 7 ; pp. 682-688
Type of Manuscript:  Special Section PAPER (Special Issue on Test and Diagnosis of VLSI)
Category: IDDQ Testing
Keyword: 
compactionIDDQ testingiterative improvement methodbridging faultATPG
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Extending Pitchmatching Algorithms to Layouts with Multiple Grid Constraints
Hiroshi MIYASHITA 
Publication:   IEICE TRANSACTIONS on Fundamentals of Electronics, Communications and Computer Sciences
Publication Date: 1996/06/25
Vol. E79-A  No. 6 ; pp. 900-909
Type of Manuscript:  PAPER
Category: VLSI Design Technology and CAD
Keyword: 
compactionpitchmatchingmultiple grid constraintsleaf cellsmacro cellsmixed-integer linear programming
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Compaction with Shape Optimization and Its Application to Layout Recycling
Kazuhisa OKADA Hidetoshi ONODERA Keikichi TAMURA 
Publication:   IEICE TRANSACTIONS on Fundamentals of Electronics, Communications and Computer Sciences
Publication Date: 1995/02/25
Vol. E78-A  No. 2 ; pp. 169-176
Type of Manuscript:  Special Section PAPER (Special Section on Analog Circuit Techniques and Computer Aided Design)
Category: 
Keyword: 
analog layoutcompactionshape optimizationlayout recycling
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A Multi-Layer Channel Router Using Simulated Annealing
Masahiko TOYONAGA Chie IWASAKI Yoshiaki SAWADA Toshiro AKINO 
Publication:   IEICE TRANSACTIONS on Fundamentals of Electronics, Communications and Computer Sciences
Publication Date: 1994/12/25
Vol. E77-A  No. 12 ; pp. 2085-2091
Type of Manuscript:  Special Section PAPER (Special Section on VLSI Design and CAD Algorithms)
Category: 
Keyword: 
channel routersimulated annealinglayer assignmentcompaction
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Procedural Detailed Compaction for the Symbolic Layout Design of CMOS Leaf Cells
Hiroshi MIYASHITA 
Publication:   IEICE TRANSACTIONS on Fundamentals of Electronics, Communications and Computer Sciences
Publication Date: 1994/11/25
Vol. E77-A  No. 11 ; pp. 1957-1969
Type of Manuscript:  PAPER
Category: Computer Aided Design (CAD)
Keyword: 
symbolic layoutcompactiondesign ruleleaf cellconstraint graph
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A preconstrained Compaction Method Applied to Direct Design-Rule Conversion of CMOS Layouts
Hiroshi MIYASHITA 
Publication:   IEICE TRANSACTIONS on Fundamentals of Electronics, Communications and Computer Sciences
Publication Date: 1994/10/25
Vol. E77-A  No. 10 ; pp. 1684-1691
Type of Manuscript:  PAPER
Category: Computer Aided Design (CAD)
Keyword: 
compactiondesign rulesconstraint graphstrongly-connected-componentscell layouts
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Optimal Constraint Graph Generation Algorithm for Layout Compaction Using Enhanced Plane-Sweep Method
Toru AWASHIMA Masao SATO Tatsuo OHTSUKI 
Publication:   IEICE TRANSACTIONS on Fundamentals of Electronics, Communications and Computer Sciences
Publication Date: 1993/04/25
Vol. E76-A  No. 4 ; pp. 507-512
Type of Manuscript:  Special Section PAPER (Special Section on Discrete Mathematics and Its Applications)
Category: 
Keyword: 
computer aided designLSI design technologylayout designcompactionplane-sweep method
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