Keyword : compact test sets


Compaction of Test Sets for Combinational Circuits Based on Symbolic Fault Simulation
Hiroyuki HIGUCHI Nagisa ISHIURA Shuzo YAJIMA 
Publication:   IEICE TRANSACTIONS on Information and Systems
Publication Date: 1993/09/25
Vol. E76-D  No. 9 ; pp. 1121-1127
Type of Manuscript:  Special Section PAPER (Special Issue on Synthesis and Verification of Hardware Design)
Category: Test
Keyword: 
test generationcombinational circuitscompact test setsbinary decision diagrams
 Summary | Full Text:PDF