Keyword : combinational circuits

Analyzing Impacts of SRAM, FF and Combinational Circuit on Chip-Level Neutron-Induced Soft Error Rate
Wang LIAO Masanori HASHIMOTO 
Publication:   
Publication Date: 2019/04/01
Vol. E102-C  No. 4 ; pp. 296-302
Type of Manuscript:  Special Section PAPER (Special Section on Solid-State Circuit Design — Architecture, Circuit, Device and Design Methodology)
Category: 
Keyword: 
soft error rate, chip-level, SRAMs, flip flops, combinational circuits, 
 Summary | Full Text:PDF
Post-BIST Fault Diagnosis for Multiple Faults
Hiroshi TAKAHASHI Yoshinobu HIGAMI Shuhei KADOYAMA Yuzo TAKAMATSU Koji YAMAZAKI Takashi AIKYO Yasuo SATO 
Publication:   IEICE TRANSACTIONS on Information and Systems
Publication Date: 2008/03/01
Vol. E91-D  No. 3 ; pp. 771-775
Type of Manuscript:  Special Section LETTER (Special Section on Test and Verification of VLSIs)
Category: 
Keyword: 
post-BIST fault diagnosis, multiple stuck-at faults, combinational circuits, pass/fail information, 
 Summary | Full Text:PDF
Fault Diagnosis on Multiple Fault Models by Using Pass/Fail Information
Yuzo TAKAMATSU Hiroshi TAKAHASHI Yoshinobu HIGAMI Takashi AIKYO Koji YAMAZAKI 
Publication:   IEICE TRANSACTIONS on Information and Systems
Publication Date: 2008/03/01
Vol. E91-D  No. 3 ; pp. 675-682
Type of Manuscript:  Special Section PAPER (Special Section on Test and Verification of VLSIs)
Category: Fault Diagnosis
Keyword: 
diagnosis, fault model, fault location, fault simulation, combinational circuits, pass/fail information, 
 Summary | Full Text:PDF
An Alternative Test Generation for Path Delay Faults by Using Ni-Detection Test Sets
Hiroshi TAKAHASHI Kewal K. SALUJA Yuzo TAKAMATSU 
Publication:   IEICE TRANSACTIONS on Information and Systems
Publication Date: 2003/12/01
Vol. E86-D  No. 12 ; pp. 2650-2658
Type of Manuscript:  Special Section PAPER (Special Issue on Dependable Computing)
Category: Test
Keyword: 
test generation, path delay faults N-propagation test-pair set, combinational circuits, 
 Summary | Full Text:PDF
EB Tester Line Delay Fault Localization Algorithm for Combinational Circuits Considering CAD Layout
Kazuhiro NOMURA Koji NAKAMAE Hiromu FUJIOKA 
Publication:   IEICE TRANSACTIONS on Information and Systems
Publication Date: 2002/10/01
Vol. E85-D  No. 10 ; pp. 1564-1570
Type of Manuscript:  Special Section PAPER (Special Issue on Test and Verification of VLSI)
Category: EB Tester
Keyword: 
EB tester, line delay fault, fault localization, layout analysis, combinational circuits, 
 Summary | Full Text:PDF
A Study for Testability of Redundant Faults in Combinational Circuits Using Delay Effects
Xiangqiu YU Hiroshi TAKAHASHI Yuzo TAKAMATSU 
Publication:   IEICE TRANSACTIONS on Information and Systems
Publication Date: 1995/07/25
Vol. E78-D  No. 7 ; pp. 822-829
Type of Manuscript:  Special Section PAPER (Special Issue on Verification, Test and Diagnosis of VLSI Systems)
Category: 
Keyword: 
test generation, combinational circuits, redundant faults, delay effect, extended seven-valued calculus, 
 Summary | Full Text:PDF
Compaction of Test Sets for Combinational Circuits Based on Symbolic Fault Simulation
Hiroyuki HIGUCHI Nagisa ISHIURA Shuzo YAJIMA 
Publication:   IEICE TRANSACTIONS on Information and Systems
Publication Date: 1993/09/25
Vol. E76-D  No. 9 ; pp. 1121-1127
Type of Manuscript:  Special Section PAPER (Special Issue on Synthesis and Verification of Hardware Design)
Category: Test
Keyword: 
test generation, combinational circuits, compact test sets, binary decision diagrams, 
 Summary | Full Text:PDF
Synthesis of Multilevel Logic Circuits from Binary Decision Diagrams
Nagisa ISHIURA 
Publication:   IEICE TRANSACTIONS on Information and Systems
Publication Date: 1993/09/25
Vol. E76-D  No. 9 ; pp. 1085-1092
Type of Manuscript:  Special Section PAPER (Special Issue on Synthesis and Verification of Hardware Design)
Category: Logic Synthesis
Keyword: 
logic synthesis, binary decision diagrams, combinational circuits, 
 Summary | Full Text:PDF
A Design Method of SFS and SCD Combinational Circuits
Shin'ichi HATAKENAKA Takashi NANYA 
Publication:   IEICE TRANSACTIONS on Information and Systems
Publication Date: 1992/11/25
Vol. E75-D  No. 6 ; pp. 819-823
Type of Manuscript:  Special Section PAPER (Special Issue on Pacific Rim International Symposium on Fault Tolerant Systems)
Category: 
Keyword: 
self-checking circuits, strongly fault-secure, strongly code-disjoint, combinational circuits, concurrent error detection, 
 Summary | Full Text:PDF
A Method of Generating Tests for Combinational Circuits with Multiple Faults
Hiroshi TAKAHASHI Nobukage IUCHI Yuzo TAKAMATSU 
Publication:   IEICE TRANSACTIONS on Information and Systems
Publication Date: 1992/07/25
Vol. E75-D  No. 4 ; pp. 569-576
Type of Manuscript:  PAPER
Category: Fault Tolerant Computing
Keyword: 
multiple faults, combinational circuits, test generation, robust tests, 
 Summary | Full Text:PDF