Keyword : coarse-grained reconfigurable architecture


Mapping Multi-Level Loop Nests onto CGRAs Using Polyhedral Optimizations
Dajiang LIU Shouyi YIN Leibo LIU Shaojun WEI 
Publication:   IEICE TRANSACTIONS on Fundamentals of Electronics, Communications and Computer Sciences
Publication Date: 2015/07/01
Vol. E98-A  No. 7 ; pp. 1419-1430
Type of Manuscript:  Special Section PAPER (Special Section on Design Methodologies for System on a Chip)
Category: 
Keyword: 
coarse-grained reconfigurable architectureloopspolyhedral modelmapping
 Summary | Full Text:PDF(2.7MB)

An Error Correction Scheme through Time Redundancy for Enhancing Persistent Soft-Error Tolerance of CGRAs
Takashi IMAGAWA Masayuki HIROMOTO Hiroyuki OCHI Takashi SATO 
Publication:   IEICE TRANSACTIONS on Electronics
Publication Date: 2015/07/01
Vol. E98-C  No. 7 ; pp. 741-750
Type of Manuscript:  PAPER
Category: Integrated Electronics
Keyword: 
coarse-grained reconfigurable architecturereliabilitytriple modular redundancyimmediate terminationerror-critical period
 Summary | Full Text:PDF(1.4MB)

Iterative Synthesis Methods Estimating Programmable-Wire Congestion in a Dynamically Reconfigurable Processor
Takao TOI Takumi OKAMOTO Toru AWASHIMA Kazutoshi WAKABAYASHI Hideharu AMANO 
Publication:   IEICE TRANSACTIONS on Fundamentals of Electronics, Communications and Computer Sciences
Publication Date: 2011/12/01
Vol. E94-A  No. 12 ; pp. 2619-2627
Type of Manuscript:  Special Section PAPER (Special Section on VLSI Design and CAD Algorithms)
Category: High-Level Synthesis and System-Level Design
Keyword: 
coarse-grained reconfigurable architecturedynamically reconfigurable processorhigh-level synthesisiterative synthesiswire delay
 Summary | Full Text:PDF(2.1MB)

An Instruction Mapping Scheme for FU Array Accelerator
Kazuhiro YOSHIMURA Takuya IWAKAMI Takashi NAKADA Jun YAO Hajime SHIMADA Yasuhiko NAKASHIMA 
Publication:   IEICE TRANSACTIONS on Information and Systems
Publication Date: 2011/02/01
Vol. E94-D  No. 2 ; pp. 286-297
Type of Manuscript:  PAPER
Category: Computer System
Keyword: 
instruction mappingFU arraycoarse-grained reconfigurable architecture
 Summary | Full Text:PDF(3.6MB)

Mapping Parallel FFT Algorithm onto SmartCell Coarse-Grained Reconfigurable Architecture
Cao LIANG Xinming HUANG 
Publication:   IEICE TRANSACTIONS on Electronics
Publication Date: 2010/03/01
Vol. E93-C  No. 3 ; pp. 407-415
Type of Manuscript:  PAPER
Category: Integrated Electronics
Keyword: 
coarse-grained reconfigurable architectureparallel FFTenergy efficiencyASICFPGADSP
 Summary | Full Text:PDF(758.6KB)