Keyword : clock tree synthesis

Layout-Driven Skewed Clock Tree Synthesis for Superconducting SFQ Circuits
Kazuyoshi TAKAGI Yuki ITO Shota TAKESHIMA Masamitsu TANAKA Naofumi TAKAGI 
Publication:   IEICE TRANSACTIONS on Electronics
Publication Date: 2011/03/01
Vol. E94-C  No. 3 ; pp. 288-295
Type of Manuscript:  Special Section PAPER (Special Section on Superconducting Signal Processing Technologies)
Category: 
Keyword: 
single-flux-quantum circuit, design methodology, clock tree synthesis, clock skew, 
 Summary | Full Text:PDF
A High-Speed and Low-Power Clock Tree Synthesis by Dynamic Clock Scheduling
Keiichi KUROKAWA Takuya YASUI Yoichi MATSUMURA Masahiko TOYONAGA Atsushi TAKAHASHI 
Publication:   IEICE TRANSACTIONS on Fundamentals of Electronics, Communications and Computer Sciences
Publication Date: 2002/12/01
Vol. E85-A  No. 12 ; pp. 2746-2755
Type of Manuscript:  Special Section PAPER (Special Section on VLSI Design and CAD Algorithms)
Category: Clock Scheduling
Keyword: 
clock scheduling, clock tree synthesis, high-speed, low power, 
 Summary | Full Text:PDF