Keyword : clock routing


Post-Routing Double-Via Insertion for X-Architecture Clock Tree Yield Improvement
Chia-Chun TSAI Chung-Chieh KUO Trong-Yen LEE 
Publication:   IEICE TRANSACTIONS on Fundamentals of Electronics, Communications and Computer Sciences
Publication Date: 2011/02/01
Vol. E94-A  No. 2 ; pp. 706-716
Type of Manuscript:  PAPER
Category: VLSI Design Technology and CAD
Keyword: 
clock routingdesign for manufacturabilitydouble viaX-architecture
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A New Clock Routing Algorithm Using Link-Edge Insertion for High Performance IC Design
Kwang-Ki RYOO Hyunchul SHIN Jong-Wha CHONG 
Publication:   IEICE TRANSACTIONS on Fundamentals of Electronics, Communications and Computer Sciences
Publication Date: 2000/06/25
Vol. E83-A  No. 6 ; pp. 1115-1122
Type of Manuscript:  Special Section PAPER (Special Section of Papers Selected from 1999 International Technical Conference on Circuits/Systems, Computers and Communications (ITC-CSCC'99))
Category: 
Keyword: 
clock routingbounded skewtopologywire sizing
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Delay and Skew Minimized Clock Tree Synthesis for Embedded Arrays
Midori TAKANO Fumihiro MINAMI Naohito KOJIMA 
Publication:   IEICE TRANSACTIONS on Information and Systems
Publication Date: 1996/10/25
Vol. E79-D  No. 10 ; pp. 1405-1409
Type of Manuscript:  Special Section PAPER (Special Issue on Synthesis and Verification of Hardware Design)
Category: Lauout Synthesis
Keyword: 
clock routingdelayskewembedded array
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