Keyword : clock network

Power and Skew Aware Point Diffusion Clock Network
Gunok JUNG Chunghee KIM Kyoungkuk CHAE Giho PARK Sung Bae PARK 
Publication:   IEICE TRANSACTIONS on Electronics
Publication Date: 2008/11/01
Vol. E91-C  No. 11 ; pp. 1832-1834
Type of Manuscript:  LETTER
Category: Integrated Electronics
clock networkskewlatencylow power
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Navigating Register Placement for Low Power Clock Network Design
Yongqiang LU Chin-Ngai SZE Xianlong HONG Qiang ZHOU Yici CAI Liang HUANG Jiang HU 
Publication:   IEICE TRANSACTIONS on Fundamentals of Electronics, Communications and Computer Sciences
Publication Date: 2005/12/01
Vol. E88-A  No. 12 ; pp. 3405-3411
Type of Manuscript:  Special Section PAPER (Special Section on VLSI Design and CAD Algorithms)
Category: Floorplan and Placement
clock networkstandard cellquadratic placementprescribed skew
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