IEICE Trans

Keyword : clock generator

A 0.5-V, 0.05-to-3.2 GHz LC-Based Clock Generator for Substituting Ring Oscillators under Low-Voltage Condition Wei DENG Kenichi OKADA Akira MATSUZAWA
Publication: IEICE TRANSACTIONS on Electronics Publication Date: 2012/07/01 Vol. E95-C No. 7 ; pp. 1285-1296 Type of Manuscript: PAPER Category: Electronic Circuits Keyword: 0.5-V, clock generator, frequency extension, low-jitter, LC-VCO,
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A Clock Generator with Clock Period, Duty-Ratio and I/Q-Balance Adjustment Capabilities for On-Chip Timing-Margin Tests Shunichi KAERIYAMA Mikihiro KAJITA Masayuki MIZUNO
Publication: IEICE TRANSACTIONS on Electronics Publication Date: 2011/01/01 Vol. E94-C No. 1 ; pp. 102-109 Type of Manuscript: PAPER Category: Integrated Electronics Keyword: clock generator, duty ratio, frequency synthesis, I/Q balance, jitter, timing margin,
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A Pseudo Fractional-N Clock Generator with 50% Duty Cycle Output Wei-Bin YANG Yu-Lung LO Ting-Sheng CHAO
Publication: IEICE TRANSACTIONS on Electronics Publication Date: 2010/03/01 Vol. E93-C No. 3 ; pp. 309-316 Type of Manuscript: Special Section PAPER (Special Section on Circuits and Design Techniques for Advanced Large Scale Integration) Category: Keyword: fractional-N, clock generator, pseudo fractional-N controller, duty cycle,
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A Low-Jitter Area-Efficient LC-VCO Based Clock Generator in 0.13-µm CMOS Joonhee LEE Sungjun KIM Sehyung JEON Woojae LEE SeongHwan CHO
Publication: IEICE TRANSACTIONS on Electronics Publication Date: 2009/04/01 Vol. E92-C No. 4 ; pp. 589-591 Type of Manuscript: LETTER Category: Electronic Circuits Keyword: clock generator, LC-VCO, area-efficient LC-VCO,
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A Low-Power Low-Noise Clock Signal Generator for Next-Generation Mobile Wireless Terminals Akihide SAI Daisuke KUROSE Takafumi YAMAJI Tetsuro ITAKURA
Publication: IEICE TRANSACTIONS on Fundamentals of Electronics, Communications and Computer Sciences Publication Date: 2008/02/01 Vol. E91-A No. 2 ; pp. 557-560 Type of Manuscript: Special Section LETTER (Special Section on Analog Circuit Techniques and Related Topics) Category: Keyword: clock generator, jitter, PLL, Analog-to-Digital Converter (ADC),
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Efficient Memory Utilization for High-Speed FPGA-Based Hardware Emulators with SDRAMs Kohei HOSOKAWA Katsunori TANAKA Yuichi NAKAMURA
Publication: IEICE TRANSACTIONS on Fundamentals of Electronics, Communications and Computer Sciences Publication Date: 2007/12/01 Vol. E90-A No. 12 ; pp. 2810-2817 Type of Manuscript: Special Section PAPER (Special Section on VLSI Design and CAD Algorithms) Category: System Level Design Keyword: FPGA-based hardware emulators, SDRAM, memory controller, clock generator,
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A PLL-Based Programmable Clock Generator with 50-to 350-MHz Oscillating Range for Video Signal Processors Junichi GOTO Masakazu YAMASHINA Toshiaki INOUE Benjamin S. SHIH Youichi KOSEKI Tadahiko HORIUCHI Nobuhisa HAMATAKE Kouichi KUMAGAI Tadayoshi ENOMOTO Hachiro YAMADA
Publication: IEICE TRANSACTIONS on Electronics Publication Date: 1994/12/25 Vol. E77-C No. 12 ; pp. 1951-1956 Type of Manuscript: Special Section PAPER (Special Issue on Multimedia, Analog and Processing LSIs) Category: Processor Interfaces Keyword: electronic circuits, clock generator, PLL, frequency multiplication, VCO, VCO gain, jitter, pull-in range, CMOS, VSP,
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