Keyword : clock and data recovery

An Injection-Controlled 10-Gb/s Burst-Mode CDR Circuit for a 1G/10G PON System
Hiroaki KATSURAI Hideki KAMITSUNA Hiroshi KOIZUMI Jun TERADA Yusuke OHTOMO Tsugumichi SHIBATA 
Publication:   IEICE TRANSACTIONS on Electronics
Publication Date: 2011/04/01
Vol. E94-C  No. 4 ; pp. 582-588
Type of Manuscript:  Special Section PAPER (Special Section on Circuits and Design Techniques for Advanced Large Scale Integration)
Category: 
Keyword: 
clock and data recovery, optical communication, receivers, burst mode, 1G/10G PON, 10G-EPON, 
 Summary | Full Text:PDF
A Multi-Band Burst-Mode Clock and Data Recovery Circuit
Che-Fu LIANG Sy-Chyuan HWU Shen-Iuan LIU 
Publication:   IEICE TRANSACTIONS on Electronics
Publication Date: 2007/04/01
Vol. E90-C  No. 4 ; pp. 802-810
Type of Manuscript:  Special Section PAPER (Special Section on Low-Power, High-Speed LSIs and Related Technologies)
Category: Analog and Communications
Keyword: 
multi-band, burst-mode, clock and data recovery, voltage-controlled oscillator, 
 Summary | Full Text:PDF
A CMOS Clock and Data Recovery Circuit with a Half-Rate Three-State Phase Detector
Ching-Yuan YANG Yu LEE Cheng-Hsing LEE 
Publication:   IEICE TRANSACTIONS on Electronics
Publication Date: 2006/06/01
Vol. E89-C  No. 6 ; pp. 746-752
Type of Manuscript:  Special Section PAPER (Special Section on Analog Circuit and Device Technologies)
Category: 
Keyword: 
phase-locked loop, phase synchronization, clock and data recovery, phase detector, 
 Summary | Full Text:PDF
A Clock and Data Recovery PLL for Variable Bit Rate NRZ Data Using Adaptive Phase Frequency Detector
Gijun IDEI Hiroaki KUNIEDA 
Publication:   IEICE TRANSACTIONS on Electronics
Publication Date: 2004/06/01
Vol. E87-C  No. 6 ; pp. 956-963
Type of Manuscript:  Special Section PAPER (Special Section on Analog Circuit and Device Technologies)
Category: 
Keyword: 
capture range, CCO, CDR, clock and data recovery, false lock, jitter, NRZ, PFD, PLL, VCO, z-domain analysis, 
 Summary | Full Text:PDF
A Giga-b/s CMOS Clock and Data Recovery Circuit with a Novel Adaptive Phase Detector
Jae-Wook LEE Cheon-O LEE Woo-Young CHOI 
Publication:   IEICE TRANSACTIONS on Communications
Publication Date: 2003/07/01
Vol. E86-B  No. 7 ; pp. 2186-2189
Type of Manuscript:  LETTER
Category: Communication Devices/Circuits
Keyword: 
clock and data recovery, phase detector, phase locked loop, 
 Summary | Full Text:PDF
A 10 Gbase Ethernet Transceiver (LAN PHY) in a 1.8 V, 0.18 µm SOI/CMOS Technology
Tsutomu YOSHIMURA Kimio UEDA Jun TAKASOH Harufusa KONDOH 
Publication:   IEICE TRANSACTIONS on Electronics
Publication Date: 2003/04/01
Vol. E86-C  No. 4 ; pp. 643-651
Type of Manuscript:  Special Section PAPER (Special Issue on High-Performance, Low-Power System LSIs and Related Technologies)
Category: Design Methods and Implementation
Keyword: 
10 Gb/s Ethernet, clock and data recovery, lock detector, SOI/CMOS process, 
 Summary | Full Text:PDF
Techniques for Widening Lock and Pull-in Ranges and Suppressing Jitter in Clock and Data Recovery ICs--Duplicated Loop Control CDR--
Keiji KISHINE Noboru ISHIHARA Haruhiko ICHINO 
Publication:   IEICE TRANSACTIONS on Electronics
Publication Date: 2001/04/01
Vol. E84-C  No. 4 ; pp. 460-469
Type of Manuscript:  PAPER
Category: Integrated Electronics
Keyword: 
clock and data recovery, PLL, duplicated loop, low jitter, 2.5-Gb/s, 
 Summary | Full Text:PDF