Keyword : clock and data recovery circuit

A New 1.25-Gb/s Burst Mode Clock and Data Recovery Circuit Using Two Digital Phase Aligners and a Phase Interpolator
Chang-Kyung SEONG Seung-Woo LEE Woo-Young CHOI 
Publication:   IEICE TRANSACTIONS on Communications
Publication Date: 2008/05/01
Vol. E91-B  No. 5 ; pp. 1397-1402
Type of Manuscript:  PAPER
Category: Devices/Circuits for Communications
burst-modeclock and data recovery circuitdigital phase alignerphase interpolator
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