Keyword : chip-level substrate coupling

Chip-Level Substrate Coupling Analysis with Reference Structures for Verification
Daisuke KOSAKA Makoto NAGATA Yoshitaka MURASAKA Atsushi IWATA 
Publication:   IEICE TRANSACTIONS on Fundamentals of Electronics, Communications and Computer Sciences
Publication Date: 2007/12/01
Vol. E90-A  No. 12 ; pp. 2651-2660
Type of Manuscript:  Special Section PAPER (Special Section on VLSI Design and CAD Algorithms)
Category: Physical Design
chip-level substrate couplingF-matrix computationslice-and-stack substrate modeling
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