Publication: IEICE TRANSACTIONS on Fundamentals of Electronics, Communications and Computer Sciences Publication Date: 2003/12/01 Vol. E86-ANo. 12 ;
pp. 3204-3207 Type of Manuscript: Special Section LETTER (Special Section on VLSI Design and CAD Algorithms) Category: IP Design Keyword: datapath design, bit-slice layout, transistor sizing, cell-base design,
Publication: IEICE TRANSACTIONS on Fundamentals of Electronics, Communications and Computer Sciences Publication Date: 2001/11/01 Vol. E84-ANo. 11 ;
pp. 2769-2777 Type of Manuscript: Special Section PAPER (Special Section on VLSI Design and CAD Algorithms) Category: Optimization of Power and Timing Keyword: transistor sizing, low power design, cell-base design, post-layout optimization, gate sizing,
