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| Keyword : cache
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Content Retrieval Method in Cooperation with CDN and Breadcrumbs-Based In-Network Guidance Method
Yutaro INABA Yosuke TANIGAWA Hideki TODE | Publication: IEICE TRANSACTIONS on Communications
Publication Date: 2016/05/01
Vol. E99-B
No. 5 ;
pp. 992-1001
Type of Manuscript:
Special Section PAPER (Special Section on Internet Architectures and Management Methods that Enable Flexible and Secure Deployment of Network Services)
Category:
Keyword:
Breadcrumbs, cache, content-oriented network, Breadcrumbs+, | | | Summary | Full Text:PDF | |
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Cache-Conscious Data Access for DBMS in Multicore Environments
Fang XI Takeshi MISHIMA Haruo YOKOTA | Publication: IEICE TRANSACTIONS on Information and Systems
Publication Date: 2015/05/01
Vol. E98-D
No. 5 ;
pp. 1001-1012
Type of Manuscript:
Special Section PAPER (Special Section on Data Engineering and Information Management)
Category:
Keyword:
multicore, OLTP, middleware, cache, | | | Summary | Full Text:PDF | |
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Bayesian Theory Based Adaptive Proximity Data Accessing for CMP Caches
Guohong LI Zhenyu LIU Sanchuan GUO Dongsheng WANG | Publication: IEICE TRANSACTIONS on Fundamentals of Electronics, Communications and Computer Sciences
Publication Date: 2013/06/01
Vol. E96-A
No. 6 ;
pp. 1293-1305
Type of Manuscript:
Special Section PAPER (Special Section on Circuit, System, and Computer Technologies)
Category:
Keyword:
Bayesian Decision, cache, multicore, | | | Summary | Full Text:PDF | |
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Evaluation of a New Power-Gating Scheme Utilizing Data Retentiveness on Caches
Kyundong KIM Seidai TAKEDA Shinobu MIWA Hiroshi NAKAMURA | Publication: IEICE TRANSACTIONS on Fundamentals of Electronics, Communications and Computer Sciences
Publication Date: 2012/12/01
Vol. E95-A
No. 12 ;
pp. 2301-2308
Type of Manuscript:
Special Section PAPER (Special Section on VLSI Design and CAD Algorithms)
Category: Logic Synthesis, Test and Verification
Keyword:
low-power, cache, leakage power, | | | Summary | Full Text:PDF | |
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Adaptive Mode Control for Low-Power Caches Based on Way-Prediction Accuracy
Hidekazu TANAKA Koji INOUE | Publication: IEICE TRANSACTIONS on Fundamentals of Electronics, Communications and Computer Sciences
Publication Date: 2005/12/01
Vol. E88-A
No. 12 ;
pp. 3274-3281
Type of Manuscript:
Special Section PAPER (Special Section on VLSI Design and CAD Algorithms)
Category: Low Power Methodology
Keyword:
low power, cache, way prediction, confidence information, | | | Summary | Full Text:PDF | |
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Quantitative Evaluation of State-Preserving Leakage Reduction Algorithm for L1 Data Caches
Reiko KOMIYA Koji INOUE Vasily G. MOSHNYAGA Kazuaki MURAKAMI | Publication: IEICE TRANSACTIONS on Fundamentals of Electronics, Communications and Computer Sciences
Publication Date: 2005/04/01
Vol. E88-A
No. 4 ;
pp. 862-868
Type of Manuscript:
Special Section PAPER (Special Section on Selected Papers from the 17th Workshop on Circuits and Systems in Karuizawa)
Category:
Keyword:
low power, cache, leakage, | | | Summary | Full Text:PDF | |
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Omitting Cache Look-up for High-Performance, Low-Power Microprocessors
Koji INOUE Vasily G. MOSHNYAGA Kazuaki MURAKAMI | Publication: IEICE TRANSACTIONS on Electronics
Publication Date: 2002/02/01
Vol. E85-C
No. 2 ;
pp. 279-287
Type of Manuscript:
Special Section PAPER (Special Issue on High-Performance and Low-Power Microprocessors)
Category: Low-Power Technologies
Keyword:
cache, low power, look up, run time, | | | Summary | Full Text:PDF | |
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Reducing Cache Energy Dissipation by Using Dual Voltage Supply
Vasily G. MOSHNYAGA Hiroshi TSUJI | Publication: IEICE TRANSACTIONS on Fundamentals of Electronics, Communications and Computer Sciences
Publication Date: 2001/11/01
Vol. E84-A
No. 11 ;
pp. 2762-2768
Type of Manuscript:
Special Section PAPER (Special Section on VLSI Design and CAD Algorithms)
Category: Optimization of Power and Timing
Keyword:
cache, processor architecture, low-power, | | | Summary | Full Text:PDF | |
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Hash-Based Query Caching Method for Distributed Web Caching in Wide Area Networks
Takuya ASAKA Hiroyoshi MIWA Yoshiaki TANAKA | Publication: IEICE TRANSACTIONS on Communications
Publication Date: 1999/06/25
Vol. E82-B
No. 6 ;
pp. 907-914
Type of Manuscript:
Special Section PAPER (Special Issue on Distributed Processing for Controlling Telecommunications Systems)
Category:
Keyword:
Web, cache, query, hash, | | | Summary | Full Text:PDF | |
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High Bandwidth, Variable Line-Size Cache Architecture for Merged DRAM/Logic LSIs
Koji INOUE Koji KAI Kazuaki MURAKAMI | Publication: IEICE TRANSACTIONS on Electronics
Publication Date: 1998/09/25
Vol. E81-C
No. 9 ;
pp. 1438-1447
Type of Manuscript:
Special Section PAPER (Special Issue on Novel VLSI Processor Architectures)
Category:
Keyword:
cache, merged DRAM/logic LSIs, memory system, | | | Summary | Full Text:PDF | |
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