IEICE Trans

Keyword : cache memory

A Conflict-Aware Capacity Control Mechanism for Deep Cache Hierarchy Jiaheng LIU Ryusuke EGAWA Hiroyuki TAKIZAWA
Publication: Publication Date: 2022/06/01 Vol. E105-D No. 6 ; pp. 1150-1163 Type of Manuscript: PAPER Category: Computer System Keyword: cache memory, multiprocessors, energy efficiency, conflict miss,
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Packet Processing Architecture with Off-Chip Last Level Cache Using Interleaved 3D-Stacked DRAM Tomohiro KORIKAWA Akio KAWABATA Fujun HE Eiji OKI
Publication: Publication Date: 2021/02/01 Vol. E104-B No. 2 ; pp. 149-157 Type of Manuscript: PAPER Category: Network System Keyword: cache memory, communication system, memory architecture, network function virtualization,
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On-Chip Cache Architecture Exploiting Hybrid Memory Structures for Near-Threshold Computing Hongjie XU Jun SHIOMI Tohru ISHIHARA Hidetoshi ONODERA
Publication: Publication Date: 2019/12/01 Vol. E102-A No. 12 ; pp. 1741-1750 Type of Manuscript: Special Section PAPER (Special Section on VLSI Design and CAD Algorithms) Category: Keyword: standard-cell memory, SRAM, near-threshold computing, cache memory, system-on-chip,
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Towards Ultra-High-Speed Cryogenic Single-Flux-Quantum Computing Koki ISHIDA Masamitsu TANAKA Takatsugu ONO Koji INOUE
Publication: Publication Date: 2018/05/01 Vol. E101-C No. 5 ; pp. 359-369 Type of Manuscript: INVITED PAPER (Special Section on Innovative Superconducting Devices Based on New Physical Phenomena) Category: Keyword: single flux quantum (SFQ), cryogenic computing, microprocessor, cache memory, Josephson junction, low-power, high-performance, energy-efficient,
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Improvement of Data Utilization Efficiency for Cache Memory by Compressing Frequent Bit Sequences Ryotaro KOBAYASHI Ikumi KANEKO Hajime SHIMADA
Publication: IEICE TRANSACTIONS on Electronics Publication Date: 2016/08/01 Vol. E99-C No. 8 ; pp. 936-946 Type of Manuscript: Special Section PAPER (Special Section on Low-Power and High-Speed Chips) Category: Keyword: cache memory, low power, frequent bit sequences,
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Short Term Cell-Flipping Technique for Mitigating SNM Degradation Due to NBTI Yuji KUNITAKE Toshinori SATO Hiroto YASUURA
Publication: IEICE TRANSACTIONS on Electronics Publication Date: 2011/04/01 Vol. E94-C No. 4 ; pp. 520-529 Type of Manuscript: Special Section PAPER (Special Section on Circuits and Design Techniques for Advanced Large Scale Integration) Category: Keyword: NBTI, SRAM, static noise margin, stress probability, register file, cache memory,
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Temperature-Aware Configurable Cache to Reduce Energy in Embedded Systems Hamid NOORI Maziar GOUDARZI Koji INOUE Kazuaki MURAKAMI
Publication: IEICE TRANSACTIONS on Electronics Publication Date: 2008/04/01 Vol. E91-C No. 4 ; pp. 418-431 Type of Manuscript: Special Section PAPER (Special Section on Advanced Technologies in Digital LSIs and Memories) Category: Keyword: temperature-aware design, cache memory, leakage current, low energy, embedded systems,
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Address Addition and Decoding without Carry Propagation Yung-Hei LEE Seung Ho HWANG
Publication: IEICE TRANSACTIONS on Information and Systems Publication Date: 1997/01/25 Vol. E80-D No. 1 ; pp. 98-100 Type of Manuscript: LETTER Category: Algorithm and Computational Complexity Keyword: decoding, cache memory, memory latency, pipelined architecture, parallel adders, carry propagation,
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An 8-mW, 8-kB Cache Memory Using an Automatic-Power-Save Architecture for Low Power RISC Microprocessors Yasuhisa SHIMAZAKI Katsuhiro NORISUE Koichiro ISHIBASHI Hideo MAEJIMA
Publication: IEICE TRANSACTIONS on Electronics Publication Date: 1996/12/25 Vol. E79-C No. 12 ; pp. 1693-1698 Type of Manuscript: Special Section PAPER (Special Issue on Low-Power LSI Technologies) Category: Keyword: RISC microprocessor, cache memory, low power,
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Hiding Data Cache Latency with Load Address Prediction Toshinori SATO Hiroshige FUJII Seigo SUZUKI
Publication: IEICE TRANSACTIONS on Information and Systems Publication Date: 1996/11/25 Vol. E79-D No. 11 ; pp. 1523-1532 Type of Manuscript: PAPER Category: Computer Systems Keyword: RISC, cache memory, load-use hazard, load latency, address prediction,
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