Keyword : cache coherence


Write Avoidance Cache Coherence Protocol for Non-volatile Memory as Last-Level Cache in Chip-Multiprocessor
Ju Hee CHOI Jong Wook KWAK Chu Shik JHON 
Publication:   IEICE TRANSACTIONS on Information and Systems
Publication Date: 2014/08/01
Vol. E97-D  No. 8 ; pp. 2166-2169
Type of Manuscript:  LETTER
Category: Computer System
Keyword: 
cache coherencenon volatile memorySTT-RAMchip multi-processor
 Summary | Full Text:PDF(1.5MB)

A 98 GMACs/W 32-Core Vector Processor in 65 nm CMOS
Xun HE Xin JIN Minghui WANG Dajiang ZHOU Satoshi GOTO 
Publication:   IEICE TRANSACTIONS on Fundamentals of Electronics, Communications and Computer Sciences
Publication Date: 2011/12/01
Vol. E94-A  No. 12 ; pp. 2609-2618
Type of Manuscript:  Special Section PAPER (Special Section on VLSI Design and CAD Algorithms)
Category: High-Level Synthesis and System-Level Design
Keyword: 
SIMDcache coherenceNoCGMACsmulticore processor
 Summary | Full Text:PDF(3.6MB)

A Next-Generation Enterprise Server System with Advanced Cache Coherence Chips
Mariko SAKAMOTO Akira KATSUNO Go SUGIZAKI Toshio YOSHIDA Aiichiro INOUE Koji INOUE Kazuaki MURAKAMI 
Publication:   IEICE TRANSACTIONS on Electronics
Publication Date: 2007/10/01
Vol. E90-C  No. 10 ; pp. 1972-1982
Type of Manuscript:  Special Section PAPER (Special Section on VLSI Technology toward Frontiers of New Market)
Category: VLSI Architecture for Communication/Server Systems
Keyword: 
enterprise server systemcache coherencedistributed shared memoryonline transaction processingperformance evaluation
 Summary | Full Text:PDF(4.9MB)

Minimizing the Directory Size for Large-Scale Shared-Memory Multiprocessors
Jinseok KONG Pen-Chung YEW Gyungho LEE 
Publication:   IEICE TRANSACTIONS on Information and Systems
Publication Date: 2005/11/01
Vol. E88-D  No. 11 ; pp. 2533-2543
Type of Manuscript:  PAPER
Category: Computer Systems
Keyword: 
cache coherencedirectory protocolmultiprocessorshared memory architecture
 Summary | Full Text:PDF(920.3KB)

Analytic Modeling of Updating Based Cache Coherent Parallel Computers
Kazuki JOE Akira FUKUDA 
Publication:   IEICE TRANSACTIONS on Information and Systems
Publication Date: 1998/06/25
Vol. E81-D  No. 6 ; pp. 504-512
Type of Manuscript:  PAPER
Category: Computer Systems
Keyword: 
parallel computerperformance predictionanalytic modelcache coherence
 Summary | Full Text:PDF(754.9KB)

Adsmith: An Object-Based Distributed Shared Memory System for Networks of Workstations
Wen-Yew LIANG Chung-Ta KING Feipei LAI 
Publication:   IEICE TRANSACTIONS on Information and Systems
Publication Date: 1997/09/25
Vol. E80-D  No. 9 ; pp. 899-908
Type of Manuscript:  Special Section PAPER (Special Issue on Architectures, Algorithms and Networks for Massively Parallel Computing)
Category: Computer Architecture
Keyword: 
distributed systemshared memorycache coherenceconsistency memory modelparallel virtual machine
 Summary | Full Text:PDF(926.5KB)

Analytic Modeling of Cache Coherence Based Parallel Computers
Kazuki JOE Akira FUKUDA 
Publication:   IEICE TRANSACTIONS on Information and Systems
Publication Date: 1996/07/25
Vol. E79-D  No. 7 ; pp. 925-935
Type of Manuscript:  PAPER
Category: Computer Systems
Keyword: 
parallel computerperformance evaluationanalytic modelcache coherence
 Summary | Full Text:PDF(935.1KB)