Keyword : built-in self-test

Universal Testing for Linear Feed-Forward/Feedback Shift Registers
Hideo FUJIWARA Katsuya FUJIWARA Toshinori HOSOKAWA 
Publication:   
Publication Date: 2020/05/01
Vol. E103-D  No. 5 ; pp. 1023-1030
Type of Manuscript:  PAPER
Category: Dependable Computing
Keyword: 
linear feed-forward shift registers, linear feedback shift registers, test generation, sequential logic, universal test, built-in self-test, secure scan design, 
 Summary | Full Text:PDF
Design for Testability That Reduces Linearity Testing Time of SAR ADCs
Tomohiko OGAWA Haruo KOBAYASHI Satoshi UEMORI Yohei TAN Satoshi ITO Nobukazu TAKAI Takahiro J. YAMAGUCHI Kiichi NIITSU 
Publication:   IEICE TRANSACTIONS on Electronics
Publication Date: 2011/06/01
Vol. E94-C  No. 6 ; pp. 1061-1064
Type of Manuscript:  BRIEF PAPER
Category: 
Keyword: 
SAR ADC, testing, DC linearity, design for testability, built-in self-test, 
 Summary | Full Text:PDF
Power-Constrained Test Synthesis and Scheduling Algorithms for Non-Scan BIST-able RTL Data Paths
Zhiqiang YOU Ken'ichi YAMAGUCHI Michiko INOUE Jacob SAVIR Hideo FUJIWARA 
Publication:   IEICE TRANSACTIONS on Information and Systems
Publication Date: 2005/08/01
Vol. E88-D  No. 8 ; pp. 1940-1947
Type of Manuscript:  PAPER
Category: Dependable Computing
Keyword: 
design for testability, RTL data path, built-in self-test, low power testing, test scheduling, 
 Summary | Full Text:PDF
Improving Random Pattern Testability with Partial Circuit Duplication Approach
Hiroshi YOKOYAMA Xiaoqing WEN Hideo TAMAMOTO 
Publication:   IEICE TRANSACTIONS on Information and Systems
Publication Date: 1998/07/25
Vol. E81-D  No. 7 ; pp. 654-659
Type of Manuscript:  Special Section PAPER (Special Issue on Test and Diagnosis of VLSI)
Category: Design for Testability
Keyword: 
partial circuit duplication, random testing, design for testability, built-in self-test, 
 Summary | Full Text:PDF
A Built-In Self-Test for ADC and DAC in a Single-Chip Speech CODEC
Eiichi TERAOKA Toru KENGAKU Ikuo YASUI Kazuyuki ISHIKAWA Takahiro MATSUO Hideyuki WAKADA Narumi SAKASHITA Yukihiko SHIMAZU Takeshi TOKUDA 
Publication:   IEICE TRANSACTIONS on Fundamentals of Electronics, Communications and Computer Sciences
Publication Date: 1997/02/25
Vol. E80-A  No. 2 ; pp. 339-345
Type of Manuscript:  Special Section PAPER (Special Section on Analog Circuit Techniques for System-on-Chip Integration)
Category: 
Keyword: 
built-in self-test, CODEC, digital signal processor, 
 Summary | Full Text:PDF
The Number of Elements in Minimum Test Set for Locally Exhaustive Testing of Combinational Circuits with Five Outputs
Tokumi YOKOHIRA Toshimi SHIMIZU Hiroyuki MICHINISHI Yuji SUGIYAMA Takuji OKAMOTO 
Publication:   IEICE TRANSACTIONS on Information and Systems
Publication Date: 1995/07/25
Vol. E78-D  No. 7 ; pp. 874-881
Type of Manuscript:  Special Section PAPER (Special Issue on Verification, Test and Diagnosis of VLSI Systems)
Category: 
Keyword: 
built-in self-test, exhaustive testing, test pattern generation, minimum test set, dependence matrix, 
 Summary | Full Text:PDF
Two-Pattern Test Capabilities of Autonomous TGP Circuits
Kiyoshi FURUYA Edward J. McCLUSKEY 
Publication:   IEICE TRANSACTIONS on Information and Systems
Publication Date: 1993/07/25
Vol. E76-D  No. 7 ; pp. 800-808
Type of Manuscript:  Special Section PAPER (Special Issue on VLSI Testing and Testable Design)
Category: 
Keyword: 
two-pattern testing, built-in self-test, TPG circuit, linear sequential circuit, transition coverage, 
 Summary | Full Text:PDF