Keyword : building block layout


A Timing-Driven Global Routing Algorithm with Pin Assignment, Block Reshaping, and Positioning for Building Block Layout
Tetsushi KOIDE Shin'ichi WAKABAYASHI 
Publication:   IEICE TRANSACTIONS on Fundamentals of Electronics, Communications and Computer Sciences
Publication Date: 1998/12/25
Vol. E81-A  No. 12 ; pp. 2476-2484
Type of Manuscript:  Special Section PAPER (Special Section on VLSI Design and CAD Algorithms)
Category: Layout Optimization
Keyword: 
building block layoutglobal routingpin assignmenttiming constraintsimulated evolution
 Summary | Full Text:PDF

A Floorplanning Method with Topological Constraint Manipulation in VLSI Building Block Layout
Tetsushi KOIDE Yoshinori KATSURA Katsumi YAMATANI Shin'ichi WAKABAYASHI Noriyoshi YOSHIDA 
Publication:   IEICE TRANSACTIONS on Fundamentals of Electronics, Communications and Computer Sciences
Publication Date: 1994/12/25
Vol. E77-A  No. 12 ; pp. 2053-2057
Type of Manuscript:  Special Section LETTER (Special Section on VLSI Design and CAD Algorithms)
Category: 
Keyword: 
building block layoutfloorplanningrelative placementtopological constraintstrong respecttentative insertionblock reshaping
 Summary | Full Text:PDF