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Architectural Choices in Large Scale ATM Switches
Jonathan TURNER Naoaki YAMANAKA | Publication: IEICE TRANSACTIONS on Communications
Publication Date: 1998/02/25
Vol. E81-B
No. 2 ;
pp. 120-137
Type of Manuscript:
INVITED PAPER (Special Issue on ATM Switching Systems for future B-ISDN)
Category:
Keyword:
ATM, switch, B-ISDN, buffer, architecture, | | | Summary | Full Text:PDF | |
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A High-Speed Tandem-Crosspoint ATM Switch Architecture with Input and Output Buffers
Eiji OKI Naoaki YAMANAKA | Publication: IEICE TRANSACTIONS on Communications
Publication Date: 1998/02/25
Vol. E81-B
No. 2 ;
pp. 215-223
Type of Manuscript:
Special Section PAPER (Special Issue on ATM Switching Systems for future B-ISDN)
Category: ATM switching architecture
Keyword:
ATM, switch, high-speed, crosspoint, buffer, | | | Summary | Full Text:PDF | |
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A High-Speed ATM Switch that Uses a Simple Retry Algorithm and Small Input Buffers
Kouichi GENOA Naoaki YAMANAKA Yukihiro DOI | Publication: IEICE TRANSACTIONS on Communications
Publication Date: 1993/07/25
Vol. E76-B
No. 7 ;
pp. 726-730
Type of Manuscript:
Special Section LETTER (Special Section of Letters Selected from the 1992 IEICE Fall Conference and the 1993 IEICE Spring Conference)
Category:
Keyword:
ATM, switch, cell loss probability, buffer, arbitration, | | | Summary | Full Text:PDF | |
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