Keyword : bit-serial


A 5.83pJ/bit/iteration High-Parallel Performance-Aware LDPC Decoder IP Core Design for WiMAX in 65nm CMOS
Xiongxin ZHAO Zhixiang CHEN Xiao PENG Dajiang ZHOU Satoshi GOTO 
Publication:   IEICE TRANSACTIONS on Fundamentals of Electronics, Communications and Computer Sciences
Publication Date: 2013/12/01
Vol. E96-A  No. 12 ; pp. 2623-2632
Type of Manuscript:  Special Section PAPER (Special Section on VLSI Design and CAD Algorithms)
Category: High-Level Synthesis and System-Level Design
Keyword: 
WiMAXbit-serialfully-parallellayered schedulingperformance awareadvanced dynamic quantizationquasi-cycliclow-density parity-check codes
 Summary | Full Text:PDF(2.2MB)

A 115 mW 1 Gbps Bit-Serial Layered LDPC Decoder for WiMAX
Xiongxin ZHAO Xiao PENG Zhixiang CHEN Dajiang ZHOU Satoshi GOTO 
Publication:   IEICE TRANSACTIONS on Fundamentals of Electronics, Communications and Computer Sciences
Publication Date: 2012/12/01
Vol. E95-A  No. 12 ; pp. 2384-2391
Type of Manuscript:  Special Section PAPER (Special Section on VLSI Design and CAD Algorithms)
Category: High-Level Synthesis and System-Level Design
Keyword: 
WiMAXbit-seriallayered schedulingQC-LDPC
 Summary | Full Text:PDF(3MB)

Bit-Serial Single Flux Quantum Microprocessor CORE
Akira FUJIMAKI Masamitsu TANAKA Takahiro YAMADA Yuki YAMANASHI Heejoung PARK Nobuyuki YOSHIKAWA 
Publication:   IEICE TRANSACTIONS on Electronics
Publication Date: 2008/03/01
Vol. E91-C  No. 3 ; pp. 342-349
Type of Manuscript:  INVITED PAPER (Special Section on Recent Progress in Superconductive Digital Electronics)
Category: 
Keyword: 
superconductormicroprocessorsingle flux quantumbit-serialLSI
 Summary | Full Text:PDF(929.4KB)

A Step-by-Step Implementation Method of the Bit-Serial Reed-Solomon Encoder
Jinsoo BAE Hiroyuki MORIKAWA 
Publication:   IEICE TRANSACTIONS on Fundamentals of Electronics, Communications and Computer Sciences
Publication Date: 2005/12/01
Vol. E88-A  No. 12 ; pp. 3672-3674
Type of Manuscript:  LETTER
Category: Coding Theory
Keyword: 
Reed-Solomon codebit-serialencoder designBerlekamp
 Summary | Full Text:PDF(230.8KB)

A New FPGA Architecture for High Performance Bit-Serial Pipeline Datapath
Akihisa OHTA Tsuyoshi ISSHIKI Hiroaki KUNIEDA 
Publication:   IEICE TRANSACTIONS on Fundamentals of Electronics, Communications and Computer Sciences
Publication Date: 2000/08/25
Vol. E83-A  No. 8 ; pp. 1663-1672
Type of Manuscript:  PAPER
Category: VLSI Design Technology and CAD
Keyword: 
FPGAbit-seriallogic block architecturerouting architecturelogic utilizationRent's rulechip scalability
 Summary | Full Text:PDF(1.6MB)