Keyword : bit-serial architecture


A Multi-Context FPGA Using Floating-Gate-MOS Functional Pass-Gates
Masanori HARIYAMA Sho OGATA Michitaka KAMEYAMA 
Publication:   IEICE TRANSACTIONS on Electronics
Publication Date: 2006/11/01
Vol. E89-C  No. 11 ; pp. 1655-1661
Type of Manuscript:  Special Section PAPER (Special Section on Novel Device Architectures and System Integration Technologies)
Category: 
Keyword: 
time-multiplexed FPGAdynamically reconfigurable architectureDPGAbit-serial architecture
 Summary | Full Text:PDF(866.4KB)

Field-Programmable VLSI Based on a Bit-Serial Fine-Grain Architecture
Masanori HARIYAMA Weisheng CHONG Michitaka KAMEYAMA 
Publication:   IEICE TRANSACTIONS on Electronics
Publication Date: 2004/11/01
Vol. E87-C  No. 11 ; pp. 1897-1902
Type of Manuscript:  Special Section PAPER (Special Section on New System Paradigms for Integrated Electronics)
Category: 
Keyword: 
reconfigurable architectureFPGAbit-serial architecture
 Summary | Full Text:PDF(530.8KB)

Architecture of a Fine-Grain Field-Programmable VLSI Based on Multiple-Valued Source-Coupled Logic
Md.Munirul HAQUE Michitaka KAMEYAMA 
Publication:   IEICE TRANSACTIONS on Electronics
Publication Date: 2004/11/01
Vol. E87-C  No. 11 ; pp. 1869-1875
Type of Manuscript:  Special Section PAPER (Special Section on New System Paradigms for Integrated Electronics)
Category: 
Keyword: 
reconfigurable processormultiple-valued logicbit-serial architecturecurrent mode logic
 Summary | Full Text:PDF(613.6KB)