IEICE Trans

Keyword : binary decision diagrams

A Study on Attractors of Generalized Asynchronous Random Boolean Networks Van Giang TRINH Kunihiko HIRAISHI
Publication: Publication Date: 2020/08/01 Vol. E103-A No. 8 ; pp. 987-994 Type of Manuscript: PAPER Category: Mathematical Systems Science Keyword: gene regulatory networks, generalized asynchronous random Boolean networks, attractors, binary decision diagrams, SAT,
	Summary \| Full Text:PDF

Exponential Lower Bounds on the Size of Variants of OBDD Representing Integer Division Takashi HORIYAMA Shuzo YAJIMA
Publication: IEICE TRANSACTIONS on Information and Systems Publication Date: 1998/08/25 Vol. E81-D No. 8 ; pp. 793-800 Type of Manuscript: PAPER Category: Algorithm and Computational Complexity Keyword: Boolean function, division, binary decision diagrams, lower bound, fooling set,
	Summary \| Full Text:PDF

A Variable Partitioning Algorithm of BDD for FPGA Technology Mapping Jie-Hong JIANG Jing-Yang JOU Juinn-Dar HUANG Jung-Shian WEI
Publication: IEICE TRANSACTIONS on Fundamentals of Electronics, Communications and Computer Sciences Publication Date: 1997/10/25 Vol. E80-A No. 10 ; pp. 1813-1819 Type of Manuscript: Special Section PAPER (Special Section on VLSI Design and CAD Algorithms) Category: Keyword: binary decision diagrams, equivalent class, Roth-Karp decomposition, LUT-based FPGA,
	Summary \| Full Text:PDF

Generalized Reed-Muller Expressions: Complexity and an Exact Minimization Algorithm Tsutomu SASAO Debatosh DEBNATH
Publication: IEICE TRANSACTIONS on Fundamentals of Electronics, Communications and Computer Sciences Publication Date: 1996/12/25 Vol. E79-A No. 12 ; pp. 2123-2130 Type of Manuscript: Special Section PAPER (Special Section on VLSI Design and CAD Algorithms) Category: Keyword: AND-EXOR, Reed-Muller expression, complexity of logic networks, logic minimization, binary decision diagrams, easily testable networks,
	Summary \| Full Text:PDF

A New Method to Represent Sets of Products: Ternary Decision Diagrams Koichi YASUOKA
Publication: IEICE TRANSACTIONS on Fundamentals of Electronics, Communications and Computer Sciences Publication Date: 1995/12/25 Vol. E78-A No. 12 ; pp. 1722-1728 Type of Manuscript: Special Section PAPER (Special Section on VLSI Design and CAD Algorithms) Category: Keyword: sum-of-products form, ringsum-products form, logic function, binary decision diagrams,
	Summary \| Full Text:PDF

Phase Optimization in Technology Mapping Yusuke MATSUNAGA
Publication: IEICE TRANSACTIONS on Fundamentals of Electronics, Communications and Computer Sciences Publication Date: 1995/12/25 Vol. E78-A No. 12 ; pp. 1735-1741 Type of Manuscript: Special Section PAPER (Special Section on VLSI Design and CAD Algorithms) Category: Keyword: logic synthesis, technology mapping, phase optimization, binary decision diagrams,
	Summary \| Full Text:PDF

A New Algorithm for Boolean Matching Utilizing Structural Information Yusuke MATSUNAGA
Publication: IEICE TRANSACTIONS on Information and Systems Publication Date: 1995/03/25 Vol. E78-D No. 3 ; pp. 219-223 Type of Manuscript: Special Section PAPER (Special Issue on Synthesis and Verification of Hardware Design) Category: Logic Synthesis Keyword: logic synthesis, technology mapping, Boolean matching, binary decision diagrams,
	Summary \| Full Text:PDF

Symbolic Scheduling Techniques Ivan P. RADIVOJEVI Forrest BREWER
Publication: IEICE TRANSACTIONS on Information and Systems Publication Date: 1995/03/25 Vol. E78-D No. 3 ; pp. 224-230 Type of Manuscript: Special Section PAPER (Special Issue on Synthesis and Verification of Hardware Design) Category: High-Level Synthesis Keyword: high level synthesis, scheduling, computer-aided design, binary decision diagrams,
	Summary \| Full Text:PDF

Compaction of Test Sets for Combinational Circuits Based on Symbolic Fault Simulation Hiroyuki HIGUCHI Nagisa ISHIURA Shuzo YAJIMA
Publication: IEICE TRANSACTIONS on Information and Systems Publication Date: 1993/09/25 Vol. E76-D No. 9 ; pp. 1121-1127 Type of Manuscript: Special Section PAPER (Special Issue on Synthesis and Verification of Hardware Design) Category: Test Keyword: test generation, combinational circuits, compact test sets, binary decision diagrams,
	Summary \| Full Text:PDF

Synthesis of Multilevel Logic Circuits from Binary Decision Diagrams Nagisa ISHIURA
Publication: IEICE TRANSACTIONS on Information and Systems Publication Date: 1993/09/25 Vol. E76-D No. 9 ; pp. 1085-1092 Type of Manuscript: Special Section PAPER (Special Issue on Synthesis and Verification of Hardware Design) Category: Logic Synthesis Keyword: logic synthesis, binary decision diagrams, combinational circuits,
	Summary \| Full Text:PDF

Analysis of the Trends in Logic Synthesis Gabrièle SAUCIER
Publication: IEICE TRANSACTIONS on Information and Systems Publication Date: 1993/09/25 Vol. E76-D No. 9 ; pp. 1006-1017 Type of Manuscript: INVITED PAPER (Special Issue on Synthesis and Verification of Hardware Design) Category: Logic Synthesis Keyword: logic synthesis, algebraic factorization, binary decision diagrams,
	Summary \| Full Text:PDF

Minimum-Width Method of Variable Ordering for Binary Decision Diagrams Shin-ichi MINATO
Publication: IEICE TRANSACTIONS on Fundamentals of Electronics, Communications and Computer Sciences Publication Date: 1992/03/25 Vol. E75-A No. 3 ; pp. 392-399 Type of Manuscript: Special Section PAPER (Special Section on the 4th Karuizawa Workshop on Circuits and Systems) Category: Keyword: binary decision diagrams, boolean function, logic synthesis, variable ordering,
	Summary \| Full Text:PDF