Keyword : binary decision diagram (BDD)


Hexagonal Binary Decision Diagram Quantum Circuit Approach for Ultra-Low Power III-V Quantum LSIs
Hideki HASEGAWA Seiya KASAI Taketomo SATO 
Publication:   IEICE TRANSACTIONS on Electronics
Publication Date: 2004/11/01
Vol. E87-C  No. 11 ; pp. 1757-1768
Type of Manuscript:  INVITED PAPER (Special Section on New System Paradigms for Integrated Electronics)
Category: 
Keyword: 
quantum LSIquantum devicesbinary decision diagram (BDD)nanostructure networkintelligent quantum (IQ) chip
 Summary | Full Text:PDF(2.7MB)

Design of Decision Diagrams with Increased Functionality of Nodes through Group Theory
Radomir S. STANKOVI Jaakko ASTOLA 
Publication:   IEICE TRANSACTIONS on Fundamentals of Electronics, Communications and Computer Sciences
Publication Date: 2003/03/01
Vol. E86-A  No. 3 ; pp. 693-703
Type of Manuscript:  PAPER
Category: VLSI Design Technology and CAD
Keyword: 
decision diagrambinary decision diagram (BDD)Fourier transformmultiplier
 Summary | Full Text:PDF(930.6KB)

Heuristics to Minimize Multiple-Valued Decision Diagrams
Hafiz Md. HASAN BABU Tsutomu SASAO 
Publication:   IEICE TRANSACTIONS on Fundamentals of Electronics, Communications and Computer Sciences
Publication Date: 2000/12/25
Vol. E83-A  No. 12 ; pp. 2498-2504
Type of Manuscript:  Special Section PAPER (Special Section on VLSI Design and CAD Algorithms)
Category: Logic Synthesis
Keyword: 
binary decision diagram (BDD)multiple-valued decision diagram (MDD)multiple-output functionmultiple-valued logicFPGA design
 Summary | Full Text:PDF(451.2KB)

A Partially Explicit Method for Efficient Symbolic Checking of Language Containment
Kiyoharu HAMAGUCHI Michiyo ICHIHARA Toshinobu KASHIWABARA 
Publication:   IEICE TRANSACTIONS on Fundamentals of Electronics, Communications and Computer Sciences
Publication Date: 1999/11/25
Vol. E82-A  No. 11 ; pp. 2455-2464
Type of Manuscript:  Special Section PAPER (Special Section on VLSI Design and CAD Algorithms)
Category: 
Keyword: 
formal verificationlanguage containmentsymbolic model checkingbinary decision diagram (BDD)ω finite automaton
 Summary | Full Text:PDF(748.1KB)

Representations of Multiple-Output Functions Using Binary Decision Diagrams for Characteristic Functions
Hafiz Md. HASAN BABU Tsutomu SASAO 
Publication:   IEICE TRANSACTIONS on Fundamentals of Electronics, Communications and Computer Sciences
Publication Date: 1999/11/25
Vol. E82-A  No. 11 ; pp. 2398-2406
Type of Manuscript:  Special Section PAPER (Special Section on VLSI Design and CAD Algorithms)
Category: 
Keyword: 
binary decision diagram (BDD)characteristic function (CF)multiple-output functionvariable orderinglogic simulationadderbit-counting functionmultiplier
 Summary | Full Text:PDF(563.6KB)

Shared Multi-Terminal Binary Decision Diagrams for Multiple-Output Functions
Hafiz Md. HASAN BABU Tsutomu SASAO 
Publication:   IEICE TRANSACTIONS on Fundamentals of Electronics, Communications and Computer Sciences
Publication Date: 1998/12/25
Vol. E81-A  No. 12 ; pp. 2545-2553
Type of Manuscript:  Special Section PAPER (Special Section on VLSI Design and CAD Algorithms)
Category: Logic Synthesis
Keyword: 
binary decision diagram (BDD)multiple-output functions clique coverTDM realizationlogic simulation
 Summary | Full Text:PDF(652.7KB)

Implicit Representation and Manipulation of Binary Decision Diagrams
Hitoshi YAMAUCHI Nagisa ISHIURA Hiromitsu TAKAHASHI 
Publication:   IEICE TRANSACTIONS on Fundamentals of Electronics, Communications and Computer Sciences
Publication Date: 1996/03/25
Vol. E79-A  No. 3 ; pp. 354-362
Type of Manuscript:  Special Section PAPER (Special Section of Selected Papers from the 8th Karuizawa Workshop on Circuits and Systems)
Category: 
Keyword: 
binary decision diagram (BDD)representation of Boolean functionslogic design verificationlogic synthesisimplicit representation of graphs
 Summary | Full Text:PDF(747KB)