Keyword : automatic synthesis

Synthesizing Pareto Efficient Intelligible State Machines from Communication Diagram
Toshiyuki MIYAMOTO 
Publication:   
Publication Date: 2017/06/01
Vol. E100-D  No. 6 ; pp. 1200-1209
Type of Manuscript:  Special Section PAPER (Special Section on Formal Approach)
Category: Formal tools
Keyword: 
unified modeling language, choreography realization problem, Petri nets, automatic synthesis, service-oriented architecture, 
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A Correctness Assurance Approach to Automatic Synthesis of Composite Web Services
Dajuan FAN Zhiqiu HUANG Lei TANG 
Publication:   IEICE TRANSACTIONS on Information and Systems
Publication Date: 2014/06/01
Vol. E97-D  No. 6 ; pp. 1535-1545
Type of Manuscript:  PAPER
Category: Data Engineering, Web Information Systems
Keyword: 
web services, composite service, FSM model, automatic synthesis, composition requirement, 
 Summary | Full Text:PDF
An Approach for Synthesizing Intelligible State Machine Models from Choreography Using Petri Nets
Toshiyuki MIYAMOTO Yasuwo HASEGAWA Hiroyuki OIMURA 
Publication:   IEICE TRANSACTIONS on Information and Systems
Publication Date: 2014/05/01
Vol. E97-D  No. 5 ; pp. 1171-1180
Type of Manuscript:  Special Section PAPER (Special Section on Formal Approach)
Category: Formal Construction
Keyword: 
unified modeling language, choreography realization problem, Petri nets, automatic synthesis, service-oriented architecture, 
 Summary | Full Text:PDF
Compact Numerical Function Generators Based on Quadratic Approximation: Architecture and Synthesis Method
Shinobu NAGAYAMA Tsutomu SASAO Jon T. BUTLER 
Publication:   IEICE TRANSACTIONS on Fundamentals of Electronics, Communications and Computer Sciences
Publication Date: 2006/12/01
Vol. E89-A  No. 12 ; pp. 3510-3518
Type of Manuscript:  Special Section PAPER (Special Section on VLSI Design and CAD Algorithms)
Category: Circuit Synthesis
Keyword: 
LUT cascades, 2nd-order Chebyshev approximation, non-uniform segmentation, NFGs, automatic synthesis, FPGA, 
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Minimizing Energy Consumption Based on Dual-Supply-Voltage Assignment and Interconnection Simplification
Masanori HARIYAMA Shigeo YAMADERA Michitaka KAMEYAMA 
Publication:   IEICE TRANSACTIONS on Electronics
Publication Date: 2006/11/01
Vol. E89-C  No. 11 ; pp. 1551-1558
Type of Manuscript:  Special Section PAPER (Special Section on Novel Device Architectures and System Integration Technologies)
Category: 
Keyword: 
automatic synthesis, scheduling, module selection, data-path design, optimization, 
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