Keyword : at-speed test


Error Identification in At-Speed Scan BIST Environment in the Presence of Circuit and Tester Speed Mismatch
Yoshiyuki NAKAMURA Thomas CLOUQUEUR Kewal K. SALUJA Hideo FUJIWARA 
Publication:   IEICE TRANSACTIONS on Information and Systems
Publication Date: 2006/03/01
Vol. E89-D  No. 3 ; pp. 1165-1172
Type of Manuscript:  PAPER
Category: Dependable Computing
Keyword: 
BISTfault diagnosiserror identificationat-speed testlow speed tester
 Summary | Full Text:PDF(462.4KB)

Delay Fault Testing of Processor Cores in Functional Mode
Virendra SINGH Michiko INOUE Kewal K. SALUJA Hideo FUJIWARA 
Publication:   IEICE TRANSACTIONS on Information and Systems
Publication Date: 2005/03/01
Vol. E88-D  No. 3 ; pp. 610-618
Type of Manuscript:  PAPER
Category: Dependable Computing
Keyword: 
processor testdelay fault testingsoftware-based self-testat-speed test
 Summary | Full Text:PDF(331.2KB)

A Design Scheme for Delay Testing of Controllers Using State Transition Information
Tsuyoshi IWAGAKI Satoshi OHTAKE Hideo FUJIWARA 
Publication:   IEICE TRANSACTIONS on Fundamentals of Electronics, Communications and Computer Sciences
Publication Date: 2004/12/01
Vol. E87-A  No. 12 ; pp. 3200-3207
Type of Manuscript:  Special Section PAPER (Special Section on VLSI Design and CAD Algorithms)
Category: Test
Keyword: 
controllerdelay faultnon-scan designinvalid test state and transition generatorat-speed test
 Summary | Full Text:PDF(463.8KB)

Non-scan Design for Testability for Synchronous Sequential Circuits Based on Fault-Oriented Conflict Analysis
Dong XIANG Shan GU Hideo FUJIWARA 
Publication:   IEICE TRANSACTIONS on Information and Systems
Publication Date: 2003/11/01
Vol. E86-D  No. 11 ; pp. 2407-2417
Type of Manuscript:  PAPER
Category: Fault Tolerance
Keyword: 
at-speed testconflictcontaining assignmentnon-scan design for testabilitysequential depth for testability
 Summary | Full Text:PDF(1.2MB)

Accomplishment of At-Speed BISR for Embedded DRAMs
Yoshihiro NAGURA Yoshinori FUJIWARA Katsuya FURUE Ryuji OHMURA Tatsunori KOMOIKE Takenori OKITAKA Tetsushi TANIZAKI Katsumi DOSAKA Kazutami ARIMOTO Yukiyoshi KODA Tetsuo TADA 
Publication:   IEICE TRANSACTIONS on Information and Systems
Publication Date: 2002/10/01
Vol. E85-D  No. 10 ; pp. 1498-1505
Type of Manuscript:  Special Section PAPER (Special Issue on Test and Verification of VLSI)
Category: BIST
Keyword: 
at-speed testBISRembedded DRAMtest cost reduction
 Summary | Full Text:PDF(2.2MB)