IEICE Trans

Keyword : at-speed test

Error Identification in At-Speed Scan BIST Environment in the Presence of Circuit and Tester Speed Mismatch Yoshiyuki NAKAMURA Thomas CLOUQUEUR Kewal K. SALUJA Hideo FUJIWARA
Publication: IEICE TRANSACTIONS on Information and Systems Publication Date: 2006/03/01 Vol. E89-D No. 3 ; pp. 1165-1172 Type of Manuscript: PAPER Category: Dependable Computing Keyword: BIST, fault diagnosis, error identification, at-speed test, low speed tester,
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Delay Fault Testing of Processor Cores in Functional Mode Virendra SINGH Michiko INOUE Kewal K. SALUJA Hideo FUJIWARA
Publication: IEICE TRANSACTIONS on Information and Systems Publication Date: 2005/03/01 Vol. E88-D No. 3 ; pp. 610-618 Type of Manuscript: PAPER Category: Dependable Computing Keyword: processor test, delay fault testing, software-based self-test, at-speed test,
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A Design Scheme for Delay Testing of Controllers Using State Transition Information Tsuyoshi IWAGAKI Satoshi OHTAKE Hideo FUJIWARA
Publication: IEICE TRANSACTIONS on Fundamentals of Electronics, Communications and Computer Sciences Publication Date: 2004/12/01 Vol. E87-A No. 12 ; pp. 3200-3207 Type of Manuscript: Special Section PAPER (Special Section on VLSI Design and CAD Algorithms) Category: Test Keyword: controller, delay fault, non-scan design, invalid test state and transition generator, at-speed test,
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Non-scan Design for Testability for Synchronous Sequential Circuits Based on Fault-Oriented Conflict Analysis Dong XIANG Shan GU Hideo FUJIWARA
Publication: IEICE TRANSACTIONS on Information and Systems Publication Date: 2003/11/01 Vol. E86-D No. 11 ; pp. 2407-2417 Type of Manuscript: PAPER Category: Fault Tolerance Keyword: at-speed test, conflict, containing assignment, non-scan design for testability, sequential depth for testability,
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Accomplishment of At-Speed BISR for Embedded DRAMs Yoshihiro NAGURA Yoshinori FUJIWARA Katsuya FURUE Ryuji OHMURA Tatsunori KOMOIKE Takenori OKITAKA Tetsushi TANIZAKI Katsumi DOSAKA Kazutami ARIMOTO Yukiyoshi KODA Tetsuo TADA
Publication: IEICE TRANSACTIONS on Information and Systems Publication Date: 2002/10/01 Vol. E85-D No. 10 ; pp. 1498-1505 Type of Manuscript: Special Section PAPER (Special Issue on Test and Verification of VLSI) Category: BIST Keyword: at-speed test, BISR, embedded DRAM, test cost reduction,
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