Keyword : at-speed scan testing

Logic-Path-and-Clock-Path-Aware At-Speed Scan Test Generation
Fuqiang LI Xiaoqing WEN Kohei MIYASE Stefan HOLST Seiji KAJIHARA 
Publication:   IEICE TRANSACTIONS on Fundamentals of Electronics, Communications and Computer Sciences
Publication Date: 2016/12/01
Vol. E99-A  No. 12 ; pp. 2310-2319
Type of Manuscript:  Special Section PAPER (Special Section on VLSI Design and CAD Algorithms)
Category: 
Keyword: 
at-speed scan testing, IR-drop, capture-power-safety, logic path, clock path, clock stretch, test quality, 
 Summary | Full Text:PDF
A GA-Based X-Filling for Reducing Launch Switching Activity toward Specific Objectives in At-Speed Scan Testing
Yuta YAMATO Xiaoqing WEN Kohei MIYASE Hiroshi FURUKAWA Seiji KAJIHARA 
Publication:   IEICE TRANSACTIONS on Information and Systems
Publication Date: 2011/04/01
Vol. E94-D  No. 4 ; pp. 833-840
Type of Manuscript:  PAPER
Category: Dependable Computing
Keyword: 
X-filling, genetic algorithm, launch switching activity, IR-drop, at-speed scan testing, 
 Summary | Full Text:PDF
A Study of Capture-Safe Test Generation Flow for At-Speed Testing
Kohei MIYASE Xiaoqing WEN Seiji KAJIHARA Yuta YAMATO Atsushi TAKASHIMA Hiroshi FURUKAWA Kenji NODA Hideaki ITO Kazumi HATAYAMA Takashi AIKYO Kewal K. SALUJA 
Publication:   IEICE TRANSACTIONS on Fundamentals of Electronics, Communications and Computer Sciences
Publication Date: 2010/07/01
Vol. E93-A  No. 7 ; pp. 1309-1318
Type of Manuscript:  PAPER
Category: VLSI Design Technology and CAD
Keyword: 
at-speed scan testing, test generation, X-bit identification, X-filling, capture-safety checking, 
 Summary | Full Text:PDF