Keyword : at-speed BIST


DFT Timing Design Methodology for Logic BIST
Yasuo SATO Motoyuki SATO Koki TSUTSUMIDA Kazumi HATAYAMA Kazuyuki NOMOTO 
Publication:   IEICE TRANSACTIONS on Fundamentals of Electronics, Communications and Computer Sciences
Publication Date: 2003/12/01
Vol. E86-A  No. 12 ; pp. 3049-3055
Type of Manuscript:  Special Section PAPER (Special Section on VLSI Design and CAD Algorithms)
Category: Timing Verification and Test Generation
Keyword: 
DFTat-speed BISTtiming designmultiple-clock
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