Publication: IEICE TRANSACTIONS on Fundamentals of Electronics, Communications and Computer Sciences
Publication Date: 2003/12/01
Vol. E86-A
No. 12 ;
pp. 3049-3055
Type of Manuscript:
Special Section PAPER (Special Section on VLSI Design and CAD Algorithms)
Category: Timing Verification and Test Generation
Keyword:
DFT, at-speed BIST, timing design, multiple-clock, |
