|
| Keyword : asynchronous
| |
| |
| |
|
Asynchronous Circuit Design on Field Programmable Gate Array Devices
Jung-Lin YANG Shin-Nung LU Pei-Hsuan YU | Publication: IEICE TRANSACTIONS on Electronics
Publication Date: 2012/04/01
Vol. E95-C
No. 4 ;
pp. 516-522
Type of Manuscript:
Special Section PAPER (Special Section on Solid-State Circuit Design – Architecture, Circuit, Device and Design Methodology)
Category:
Keyword:
asynchronous, bundled-data, burst-mode, extended burst-mode, FPGA, generalized C-element, HDL, self-timed, | | | Summary | Full Text:PDF | |
| |
|
Iterative Algorithm for Reducing the Peak-to-Average Power Ratio of Feedback-Controlled Multitone-Hopping CDMA Signals
Kazuki CHIBA Masanori HAMAMURA | Publication: IEICE TRANSACTIONS on Communications
Publication Date: 2010/11/01
Vol. E93-B
No. 11 ;
pp. 3072-3082
Type of Manuscript:
PAPER
Category: Wireless Communication Technologies
Keyword:
CDMA, asynchronous, multipath, feedback, multitone, PAR, | | | Summary | Full Text:PDF | |
|
Multitone-Hopping CDMA Using Feedback-Controlled Hopping Pattern for Decentralized Multiple Access
Kazuki CHIBA Masanori HAMAMURA | Publication: IEICE TRANSACTIONS on Fundamentals of Electronics, Communications and Computer Sciences
Publication Date: 2008/12/01
Vol. E91-A
No. 12 ;
pp. 3723-3730
Type of Manuscript:
Special Section PAPER (Special Section on Signal Design and its Applications in Communications)
Category: Spread Spectrum Communications
Keyword:
CDMA, decentralized, asynchronous, multipath, feedback, multitone, | | | Summary | Full Text:PDF | |
| |
| |
| |
| |
| |
| |
| |
|
High-Level Synthesis of Pipelined Circuits from Modular Queue-Based Specifications
Maria-Cristina MARINESCU Martin RINARD | Publication: IEICE TRANSACTIONS on Fundamentals of Electronics, Communications and Computer Sciences
Publication Date: 2001/11/01
Vol. E84-A
No. 11 ;
pp. 2655-2664
Type of Manuscript:
Special Section PAPER (Special Section on VLSI Design and CAD Algorithms)
Category: High Level Synthesis
Keyword:
asynchronous, modular, pipeline, term rewriting system, | | | Summary | Full Text:PDF | |
| |
|
Parallel Test Structure in Latch Based Asynchronous Pipeline
Jing-ling YANG Chiu-sing CHOY Cheong-Fat CHAN | Publication: IEICE TRANSACTIONS on Fundamentals of Electronics, Communications and Computer Sciences
Publication Date: 1999/11/25
Vol. E82-A
No. 11 ;
pp. 2527-2529
Type of Manuscript:
Special Section LETTER (Special Section on VLSI Design and CAD Algorithms)
Category:
Keyword:
asynchronous, pipeline, event logic, latch, test, | | | Summary | Full Text:PDF | |
|
Quasi-Optimum Multiuser Detector Using Co-Channel Interference Cancellation Technique in Asynchronous DS/CDMA
Masatsugu TAKEUCHI Shin'ichi TACHIKAWA | Publication: IEICE TRANSACTIONS on Fundamentals of Electronics, Communications and Computer Sciences
Publication Date: 1997/07/25
Vol. E80-A
No. 7 ;
pp. 1211-1217
Type of Manuscript:
Special Section PAPER (Special Section on Multi-dimensional Mobile Information Network)
Category:
Keyword:
CDMA, asynchronous, co-channel interference, multiuser, | | | Summary | Full Text:PDF | |
|
Completion-Detection Techniques for Asynchronous Circuits
Eckhard GRASS Viv BARTLETT Izzet KALE | Publication: IEICE TRANSACTIONS on Information and Systems
Publication Date: 1997/03/25
Vol. E80-D
No. 3 ;
pp. 344-350
Type of Manuscript:
Special Section PAPER (Special Issue on Asynchronous Circuit and System Design)
Category: Completion-Detection & Checking
Keyword:
self-timing, asynchronous, completion detection, | | | Summary | Full Text:PDF | |
| |
|
|