Keyword : asynchronous circuits


Conversion from Synchronous RTL Models to Asynchronous RTL Models
Shogo SEMBA Hiroshi SAITO 
Publication:   
Publication Date: 2019/07/01
Vol. E102-A  No. 7 ; pp. 904-913
Type of Manuscript:  Special Section PAPER (Special Section on Design Methodologies for System on a Chip)
Category: 
Keyword: 
asynchronous circuitsRTL designconversionXML
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Novel Implementation Method of Multiple-Way Asynchronous Arbiters
Masashi IMAI Tomohiro YONEDA 
Publication:   IEICE TRANSACTIONS on Fundamentals of Electronics, Communications and Computer Sciences
Publication Date: 2015/07/01
Vol. E98-A  No. 7 ; pp. 1519-1528
Type of Manuscript:  PAPER
Category: VLSI Design Technology and CAD
Keyword: 
N-way asynchronous arbitersasynchronous circuitsmutual exclusion elementsrectangle mesh arbitertoken-ring arbiter
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A Low EMI Circuit Design with Asynchronous Multi-Frequency Clocking
Jeong-Gun LEE 
Publication:   IEICE TRANSACTIONS on Electronics
Publication Date: 2014/12/01
Vol. E97-C  No. 12 ; pp. 1158-1161
Type of Manuscript:  BRIEF PAPER
Category: Electronic Circuits
Keyword: 
electromagnetic interferenceEMImulti-frequency clockingasynchronous circuits
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Asynchronous Stochastic Decoding of LDPC Codes: Algorithm and Simulation Model
Naoya ONIZAWA Warren J. GROSS Takahiro HANYU Vincent C. GAUDET 
Publication:   IEICE TRANSACTIONS on Information and Systems
Publication Date: 2014/09/01
Vol. E97-D  No. 9 ; pp. 2286-2295
Type of Manuscript:  Special Section PAPER (Special Section on Multiple-Valued Logic and VLSI Computing)
Category: VLSI Architecture
Keyword: 
forward error correction (FEC)stochastic computationasynchronous circuits
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Long-Range Asynchronous On-Chip Link Based on Multiple-Valued Single-Track Signaling
Naoya ONIZAWA Atsushi MATSUMOTO Takahiro HANYU 
Publication:   IEICE TRANSACTIONS on Fundamentals of Electronics, Communications and Computer Sciences
Publication Date: 2012/06/01
Vol. E95-A  No. 6 ; pp. 1018-1029
Type of Manuscript:  PAPER
Category: Circuit Theory
Keyword: 
delay-insensitiveasynchronous circuitsmultiple-valued current-mode (MVCM) circuitsNetwork-on-Chip (NoC)communication link
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Integration of Behavioral Synthesis and Floorplanning for Asynchronous Circuits with Bundled-Data Implementation
Naohiro HAMADA Hiroshi SAITO 
Publication:   IEICE TRANSACTIONS on Electronics
Publication Date: 2012/04/01
Vol. E95-C  No. 4 ; pp. 506-515
Type of Manuscript:  Special Section PAPER (Special Section on Solid-State Circuit Design – Architecture, Circuit, Device and Design Methodology)
Category: 
Keyword: 
asynchronous circuitsbehavioral synthesisfloorplanning
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Highly Reliable Multiple-Valued One-Phase Signalling for an Asynchronous On-Chip Communication Link
Naoya ONIZAWA Takahiro HANYU 
Publication:   IEICE TRANSACTIONS on Information and Systems
Publication Date: 2010/08/01
Vol. E93-D  No. 8 ; pp. 2089-2099
Type of Manuscript:  Special Section PAPER (Special Section on Multiple-Valued Logic and VLSI Computing)
Category: Multiple-Valued VLSI Technology
Keyword: 
delay-insensitiveasynchronous circuitsmultiple-valued current-mode (MVCM) circuitsNetwork-on-Chip (NoC)communication link
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Ultra Low Power Delay Element with Post-Chip Adjustable Ability
Jung-Lin YANG Chih-Wei CHAO 
Publication:   IEICE TRANSACTIONS on Fundamentals of Electronics, Communications and Computer Sciences
Publication Date: 2009/12/01
Vol. E92-A  No. 12 ; pp. 3381-3389
Type of Manuscript:  PAPER
Category: VLSI Design Technology and CAD
Keyword: 
asynchronous circuitsbundled-datadelay-elementself-timedlow power
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A Conservative Framework for Safety-Failure Checking
Frederic BEAL Tomohiro YONEDA Chris J. MYERS 
Publication:   IEICE TRANSACTIONS on Information and Systems
Publication Date: 2008/03/01
Vol. E91-D  No. 3 ; pp. 642-654
Type of Manuscript:  Special Section PAPER (Special Section on Test and Verification of VLSIs)
Category: Verification and Timing Analysis
Keyword: 
asynchronous circuitsspeed-independent circuitssafety-failure checkinghazard checkingformal verificationover-approximations
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Scheduling Methods for Asynchronous Circuits with Bundled-Data Implementations Based on the Approximation of Start Times
Hiroshi SAITO Naohiro HAMADA Nattha JINDAPETCH Tomohiro YONEDA Chris MYERS Takashi NANYA 
Publication:   IEICE TRANSACTIONS on Fundamentals of Electronics, Communications and Computer Sciences
Publication Date: 2007/12/01
Vol. E90-A  No. 12 ; pp. 2790-2799
Type of Manuscript:  Special Section PAPER (Special Section on VLSI Design and CAD Algorithms)
Category: System Level Design
Keyword: 
asynchronous circuitsschedulingstart timesand control steps
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A Cost-Effective Handshake Protocol and Its Implementation for Bundled-Data Asynchronous Circuits
Masakazu SHIMIZU Koki ABE 
Publication:   IEICE TRANSACTIONS on Fundamentals of Electronics, Communications and Computer Sciences
Publication Date: 2006/01/01
Vol. E89-A  No. 1 ; pp. 280-287
Type of Manuscript:  PAPER
Category: VLSI Design Technology and CAD
Keyword: 
asynchronous circuitsbundled-data stylehandshake protocolslow power
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Eliminating Isochronic-Fork Constraints in Quasi-Delay-Insensitive Circuits
Nattha SRETASEREEKUL Takashi NANYA 
Publication:   IEICE TRANSACTIONS on Fundamentals of Electronics, Communications and Computer Sciences
Publication Date: 2003/04/01
Vol. E86-A  No. 4 ; pp. 900-907
Type of Manuscript:  PAPER
Category: VLSI Design Technology and CAD
Keyword: 
isochronic forksasynchronous circuitsquasi-delay-insensitive circuits
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High-Level Test Generation for Asynchronous Circuits from Signal Transition Graph
Eunjung OH Soo-Hyun KIM Dong-Ik LEE Ho-Yong CHOI 
Publication:   IEICE TRANSACTIONS on Fundamentals of Electronics, Communications and Computer Sciences
Publication Date: 2002/12/01
Vol. E85-A  No. 12 ; pp. 2674-2683
Type of Manuscript:  Special Section PAPER (Special Section on VLSI Design and CAD Algorithms)
Category: Test Generation
Keyword: 
asynchronous circuitsATPGSTG
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Framework of Timed Trace Theoretic Verification Revisited
Bin ZHOU Tomohiro YONEDA Chris MYERS 
Publication:   IEICE TRANSACTIONS on Information and Systems
Publication Date: 2002/10/01
Vol. E85-D  No. 10 ; pp. 1595-1604
Type of Manuscript:  Special Section PAPER (Special Issue on Test and Verification of VLSI)
Category: Verification
Keyword: 
timed trace theorytrace structurestime Petri netsformal verificationasynchronous circuits
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An Algebraic Specification of a Daisy Chain Arbiter
Yu Rong HOU Atsushi OHNISHI Yuji SUGIYAMA Takuji OKAMOTO 
Publication:   IEICE TRANSACTIONS on Information and Systems
Publication Date: 1992/11/25
Vol. E75-D  No. 6 ; pp. 778-784
Type of Manuscript:  Special Section PAPER (Special Issue on Pacific Rim International Symposium on Fault Tolerant Systems)
Category: 
Keyword: 
specificationalgebraic methodasynchronous circuitsarbiter
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