IEICE Trans

Keyword : asynchronous circuit

Asynchronous Circuit Designs on an FPGA for Targeting a Power/Energy Efficient SoC Jeong-Gun LEE Myeong-Hoon OH
Publication: IEICE TRANSACTIONS on Electronics Publication Date: 2014/04/01 Vol. E97-C No. 4 ; pp. 253-263 Type of Manuscript: Special Section PAPER (Special Section on Solid-State Circuit Design,---,Architecture, Circuit, Device and Design Methodology) Category: Keyword: asynchronous circuit, FPGA device, MIPS processor, low power,
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Architecture of an Asynchronous FPGA for Handshake-Component-Based Design Yoshiya KOMATSU Masanori HARIYAMA Michitaka KAMEYAMA
Publication: IEICE TRANSACTIONS on Information and Systems Publication Date: 2013/08/01 Vol. E96-D No. 8 ; pp. 1632-1644 Type of Manuscript: Special Section PAPER (Special Section on Reconfigurable Systems) Category: Architecture Keyword: FPGA, reconfigurable LSI, self-timed circuit, asynchronous circuit,
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A Self-Timed SRAM Design for Average-Case Performance Je-Hoon LEE Young-Jun SONG Sang-Choon KIM
Publication: IEICE TRANSACTIONS on Information and Systems Publication Date: 2011/08/01 Vol. E94-D No. 8 ; pp. 1547-1556 Type of Manuscript: PAPER Category: Computer System Keyword: asynchronous circuit, SRAM, self-timed logic, memory segmentation,
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Dynamically Reconfigurable Logic LSI: PCA-2 Hideyuki ITO Ryusuke KONISHI Hiroshi NAKADA Hideyuki TSUBOI Yuichi OKUYAMA Akira NAGOYA
Publication: IEICE TRANSACTIONS on Information and Systems Publication Date: 2004/08/01 Vol. E87-D No. 8 ; pp. 2011-2020 Type of Manuscript: Special Section PAPER (Special Section on Reconfigurable Systems) Category: Recornfigurable Systems Keyword: dynamically reconfigurable hardware, autonomous reconfiguration, asynchronous circuit, parallel computing,
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A Specification Style of Four-Phase Handshaking Asynchronous Controllers and the Optimization of Its Return-to-Zero Phase Rafael K. MORIZAWA Takashi NANYA
Publication: IEICE TRANSACTIONS on Fundamentals of Electronics, Communications and Computer Sciences Publication Date: 2000/12/25 Vol. E83-A No. 12 ; pp. 2446-2455 Type of Manuscript: Special Section PAPER (Special Section on VLSI Design and CAD Algorithms) Category: VLSI Design Methodology Keyword: asynchronous circuit, asynchronous specification, logic synthesis, CAD tool,
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Translating Concurrent Programs into Speed-Independent Circuits through Petri Net Transformations Dong-Hoon YOO Dong-Ik LEE
Publication: IEICE TRANSACTIONS on Fundamentals of Electronics, Communications and Computer Sciences Publication Date: 2000/11/25 Vol. E83-A No. 11 ; pp. 2203-2211 Type of Manuscript: Special Section PAPER (Special Section on Concurrent Systems Technology) Category: Keyword: asynchronous circuit, speed-independent circuit, concurrent programming, Petri net, synthesis,
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Verification of Scalable-Delay-Insensitive Asynchronous Circuits Atsushi YAMAZAKI Hiroshi RYU Tomohiro YONEDA
Publication: IEICE TRANSACTIONS on Information and Systems Publication Date: 1999/03/25 Vol. E82-D No. 3 ; pp. 701-703 Type of Manuscript: LETTER Category: Fault Tolerant Computing Keyword: formal verification, asynchronous circuit, SDI model, bounded delay model,
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A Floating-Point Divider Using Redundant Binary Circuits and an Asynchronous Clock Scheme Hiroaki SUZUKI Hiroshi MAKINO Koichiro MASHIKO
Publication: IEICE TRANSACTIONS on Electronics Publication Date: 1999/01/25 Vol. E82-C No. 1 ; pp. 105-110 Type of Manuscript: PAPER Category: Electronic Circuits Keyword: divider, floating-point execution, redundant binary circuits, asynchronous circuit, self-timed circuit,
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On Deriving Logic Functions of Asynchronous Circuits by STG Unfoldings Toshiyuki MIYAMOTO Sadatoshi KUMAGAI
Publication: IEICE TRANSACTIONS on Information and Systems Publication Date: 1997/03/25 Vol. E80-D No. 3 ; pp. 336-343 Type of Manuscript: Special Section PAPER (Special Issue on Asynchronous Circuit and System Design) Category: Synthesis Keyword: signal transition graph, occurrence net, asynchronous circuit, derive logic functions, state space explosion, speed independence,
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Petrify: A Tool for Manipulating Concurrent Specifications and Synthesis of Asynchronous Controllers Jordi CORTADELLA Michael KISHINEVSKY Alex KONDRATYEV Luciano LAVAGNO Alexandre YAKOVLEV
Publication: IEICE TRANSACTIONS on Information and Systems Publication Date: 1997/03/25 Vol. E80-D No. 3 ; pp. 315-325 Type of Manuscript: Special Section PAPER (Special Issue on Asynchronous Circuit and System Design) Category: Synthesis Keyword: asynchronous circuit, speed independence, technology mapping, Petri net, event insertion,
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An Efficient Algorithm for Deriving Logic Functions of Asynchronous Circuits Toshiyuki MIYAMOTO Sadatoshi KUMAGAI
Publication: IEICE TRANSACTIONS on Fundamentals of Electronics, Communications and Computer Sciences Publication Date: 1996/06/25 Vol. E79-A No. 6 ; pp. 818-824 Type of Manuscript: Special Section PAPER (Special Section of Papers Selected from 1995 Joint Technical Conference on Circuits/Systems, Computers and Communications (JTC-CSCC '95)) Category: Keyword: signal transition graph, occurrence net, asynchronous circuit, derive logic functions, dvoidance of state space explosion,
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An Efficient State Space Search for the Synthesis of Asynchronous Circuits by Subspace Construction Toshiyuki MIYAMOTO Dong-Ik LEE Sadatoshi KUMAGAI
Publication: IEICE TRANSACTIONS on Fundamentals of Electronics, Communications and Computer Sciences Publication Date: 1995/11/25 Vol. E78-A No. 11 ; pp. 1504-1510 Type of Manuscript: Special Section PAPER (Special Section on Net Theory and Its Applications to Discrete Event System Design) Category: Keyword: signal transition graph, occurrence net, asynchronous circuit, derive logic functions, state space explosion,
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