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| Keyword : area-efficient
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A 0.37mm2 Fully-Integrated Wide Dynamic Range Sub-GHz Receiver Front-End without Off-Chip Matching Components
Yuncheng ZHANG Bangan LIU Teruki SOMEYA Rui WU Junjun QIU Atsushi SHIRANE Kenichi OKADA | Publication:
Publication Date: 2022/07/01
Vol. E105-C
No. 7 ;
pp. 334-342
Type of Manuscript:
Special Section PAPER (Special Section on Solid-State Circuit Design — Architecture, Circuit, Device and Design Methodology)
Category:
Keyword:
receiver, area-efficient, impedance matching, dynamic range, mixer-first, low-power, wireless, Sub-GHz, IoT, 5G, CMOS, | | | Summary | Full Text:PDF(1.8MB) | |
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A Low-Cost VLSI Architecture of Multiple-Size IDCT for H.265/HEVC
Heming SUN Dajiang ZHOU Peilin LIU Satoshi GOTO | Publication: IEICE TRANSACTIONS on Fundamentals of Electronics, Communications and Computer Sciences
Publication Date: 2014/12/01
Vol. E97-A
No. 12 ;
pp. 2467-2476
Type of Manuscript:
Special Section PAPER (Special Section on VLSI Design and CAD Algorithms)
Category: High-Level Synthesis and System-Level Design
Keyword:
HEVC, IDCT, SRAM, area-efficient, video coding, | | | Summary | Full Text:PDF(3.1MB) | |
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