Keyword : area–power–delay tradeoff

Experiments with Power Optimization in Gate Sizing
Guangqiu CHEN Hidetoshi ONODERA Keikichi TAMARU 
Publication:   IEICE TRANSACTIONS on Fundamentals of Electronics, Communications and Computer Sciences
Publication Date: 1994/11/25
Vol. E77-A  No. 11 ; pp. 1913-1916
Type of Manuscript:  Special Section LETTER (Special Section of Letters Selected from the 1994 IEICE Spring Conference)
low power designpower dissipationgate sizingarea–power–delay tradeoff
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