Keyword : architecture


An Optimization Algorithm to Build Low Congestion Multi-Ring Topology for Optical Network-on-Chip
Lijing ZHU Kun WANG Duan ZHOU Liangkai LIU Huaxi GU 
Publication:   
Publication Date: 2018/07/01
Vol. E101-D  No. 7 ; pp. 1835-1842
Type of Manuscript:  PAPER
Category: Fundamentals of Information Systems
Keyword: 
optical interconnectNoCarchitecturecongestion
 Summary | Full Text:PDF

High-Speed Design of Conflictless Name Lookup and Efficient Selective Cache on CCN Router
Atsushi OOKA Shingo ATA Kazunari INOUE Masayuki MURATA 
Publication:   IEICE TRANSACTIONS on Communications
Publication Date: 2015/04/01
Vol. E98-B  No. 4 ; pp. 607-620
Type of Manuscript:  PAPER
Category: Network
Keyword: 
future networkscontent-centric networkingarchitecturerouter hardwarecontent-addressable memorybloom filter
 Summary | Full Text:PDF

Physical Architecture and Model-Based Evaluation of Electric Power System with Multiple Homes
Yoshihiko SUSUKI Ryoya KAZAOKA Takashi HIKIHARA 
Publication:   IEICE TRANSACTIONS on Fundamentals of Electronics, Communications and Computer Sciences
Publication Date: 2013/08/01
Vol. E96-A  No. 8 ; pp. 1703-1711
Type of Manuscript:  PAPER
Category: Nonlinear Problems
Keyword: 
power systemarchitecturemodelbifurcationuncertaintysystem-level design
 Summary | Full Text:PDF

Low Complexity Filter Architecture for ATSC Terrestrial Broadcasting DTV Systems
Yong-Kyu KIM Chang-Seok CHOI Hanho LEE 
Publication:   IEICE TRANSACTIONS on Fundamentals of Electronics, Communications and Computer Sciences
Publication Date: 2011/03/01
Vol. E94-A  No. 3 ; pp. 937-945
Type of Manuscript:  PAPER
Category: VLSI Design Technology and CAD
Keyword: 
digital signal processing (DSP)FIRfilterarchitecturecubic splineinterpolationdigital TV (DTV)
 Summary | Full Text:PDF

Coexistence of Dynamic Spectrum Access Based Heterogeneous Networks
Chen SUN Yohannes D. ALEMSEGED HaNguyen TRAN Hiroshi HARADA 
Publication:   IEICE TRANSACTIONS on Communications
Publication Date: 2010/12/01
Vol. E93-B  No. 12 ; pp. 3293-3301
Type of Manuscript:  Special Section PAPER (Special Section on Wireless Distributed Networks)
Category: 
Keyword: 
heterogeneous networkscognitive radio system (CRS)dynamic spectrum access (DSA)coexistencearchitecturehidden nodequality of coexistence (QoC)
 Summary | Full Text:PDF

High-Speed Two-Parallel Concatenated BCH-Based Super-FEC Architecture for Optical Communications
Sangho YOON Hanho LEE Kihoon LEE 
Publication:   IEICE TRANSACTIONS on Fundamentals of Electronics, Communications and Computer Sciences
Publication Date: 2010/04/01
Vol. E93-A  No. 4 ; pp. 769-777
Type of Manuscript:  PAPER
Category: VLSI Design Technology and CAD
Keyword: 
concatenated BCH codeFECarchitectureoptical
 Summary | Full Text:PDF

Area-Time Efficient Modulo 2n-1 Adder Design Using Hybrid Carry Selection
Su-Hon LIN Ming-Hwa SHEU 
Publication:   IEICE TRANSACTIONS on Information and Systems
Publication Date: 2008/02/01
Vol. E91-D  No. 2 ; pp. 361-362
Type of Manuscript:  LETTER
Category: Computer Components
Keyword: 
residue number systemhybrid carry selectionmodulo 2n-1 adderarchitecture
 Summary | Full Text:PDF

Towards a Service Oriented Internet
Jaideep CHANDRASHEKAR Zhi-Li ZHANG Zhenhai DUAN Y. Thomas HOU 
Publication:   IEICE TRANSACTIONS on Communications
Publication Date: 2006/09/01
Vol. E89-B  No. 9 ; pp. 2292-2299
Type of Manuscript:  INVITED PAPER (Special Section on Networking Technologies for Overlay Networks)
Category: 
Keyword: 
service-orientedoverlaysarchitecture
 Summary | Full Text:PDF

An Embedded Processor Core for Consumer Appliances with 2.8GFLOPS and 36 M Polygons/s FPU
Fumio ARAKAWA Motokazu OZAWA Osamu NISHII Toshihiro HATTORI Takeshi YOSHINAGA Tomoichi HAYASHI Yoshikazu KIYOSHIGE Takashi OKADA Masakazu NISHIBORI Tomoyuki KODAMA Tatsuya KAMEI Makoto ISHIKAWA 
Publication:   IEICE TRANSACTIONS on Fundamentals of Electronics, Communications and Computer Sciences
Publication Date: 2004/12/01
Vol. E87-A  No. 12 ; pp. 3068-3074
Type of Manuscript:  Special Section PAPER (Special Section on VLSI Design and CAD Algorithms)
Category: System Level Design
Keyword: 
embedded processorarchitectureFPUpipeline
 Summary | Full Text:PDF

A Low-Power Architecture for Extended Finite State Machines Using Input Gating
Shi-Yu HUANG Chien-Jyh LIU 
Publication:   IEICE TRANSACTIONS on Fundamentals of Electronics, Communications and Computer Sciences
Publication Date: 2004/12/01
Vol. E87-A  No. 12 ; pp. 3109-3115
Type of Manuscript:  Special Section PAPER (Special Section on VLSI Design and CAD Algorithms)
Category: Logic Synthesis
Keyword: 
low-powerarchitectureVLSI designFSMgatingsynthesis
 Summary | Full Text:PDF

Integrated Development Environment for Knowledge-Based Systems and Its Practical Application
Keiichi KATAMINE Masanobu UMEDA Isao NAGASAWA Masaaki HASHIMOTO 
Publication:   IEICE TRANSACTIONS on Information and Systems
Publication Date: 2004/04/01
Vol. E87-D  No. 4 ; pp. 877-885
Type of Manuscript:  Special Section PAPER (Special Section on Knowledge-Based Software Engineering)
Category: Knowledge Engineering and Robotics
Keyword: 
development environmentarchitecturepractical applicationknowledge description languageknowledge-based system
 Summary | Full Text:PDF

Hardware-Efficient Architecture Design for Zerotree Coding in MPEG-4 Still Texture Coder
Chung-Jr LIAN Zhong-Lan YANG Hao-Chieh CHANG Liang-Gee CHEN 
Publication:   IEICE TRANSACTIONS on Fundamentals of Electronics, Communications and Computer Sciences
Publication Date: 2003/02/01
Vol. E86-A  No. 2 ; pp. 472-479
Type of Manuscript:  PAPER
Category: VLSI Design Technology and CAD
Keyword: 
MPEG-4still texture codingzerotreearchitecture
 Summary | Full Text:PDF

An Algorithm and a Flexible Architecture for Fast Block-Matching Motion Estimation
Jinku CHOI Nozomu TOGAWA Masao YANAGISAWA Tatsuo OHTSUKI 
Publication:   IEICE TRANSACTIONS on Fundamentals of Electronics, Communications and Computer Sciences
Publication Date: 2002/12/01
Vol. E85-A  No. 12 ; pp. 2603-2611
Type of Manuscript:  Special Section PAPER (Special Section on VLSI Design and CAD Algorithms)
Category: VLSI Design
Keyword: 
motion estimationblock-matchingalgorithmarchitectureVHDL
 Summary | Full Text:PDF

Performance Estimation at Architecture Level for Embedded Systems
Hiroshi MIZUNO Hiroyuki KOBAYASHI Takao ONOYE Isao SHIRAKAWA 
Publication:   IEICE TRANSACTIONS on Fundamentals of Electronics, Communications and Computer Sciences
Publication Date: 2002/12/01
Vol. E85-A  No. 12 ; pp. 2636-2644
Type of Manuscript:  Special Section PAPER (Special Section on VLSI Design and CAD Algorithms)
Category: Performance Estimation
Keyword: 
power dissipationarchitectureembedded systemco-design
 Summary | Full Text:PDF

A New Processor Architecture for Digital Signal Transport Systems
Minoru INAMORI Kenji ISHII Akihiro TSUTSUI Kazuhiro SHIRAKAWA Toshiaki MIYAZAKI Hiroshi NAKADA 
Publication:   IEICE TRANSACTIONS on Electronics
Publication Date: 1998/09/25
Vol. E81-C  No. 9 ; pp. 1408-1415
Type of Manuscript:  Special Section PAPER (Special Issue on Novel VLSI Processor Architectures)
Category: 
Keyword: 
processorVLSIprotocol processingarchitecture
 Summary | Full Text:PDF

Architectural Choices in Large Scale ATM Switches
Jonathan TURNER Naoaki YAMANAKA 
Publication:   IEICE TRANSACTIONS on Communications
Publication Date: 1998/02/25
Vol. E81-B  No. 2 ; pp. 120-137
Type of Manuscript:  INVITED PAPER (Special Issue on ATM Switching Systems for future B-ISDN)
Category: 
Keyword: 
ATMswitchB-ISDNbufferarchitecture
 Summary | Full Text:PDF

Design and Architecture for Low-Power/High-Speed RISC Microprocessor: SuperH
Hideo MAEJIMA Masahiro KAINAGA Kunio UCHIYAMA 
Publication:   IEICE TRANSACTIONS on Electronics
Publication Date: 1997/12/25
Vol. E80-C  No. 12 ; pp. 1539-1545
Type of Manuscript:  INVITED PAPER (Special Issue on Low-Power and High-Speed LSI Technologies)
Category: 
Keyword: 
RISCarchitecturelow powerhigh speedmicroprocessor
 Summary | Full Text:PDF

A Functional Block Hardware Architecture for Switching Systems
Hitoshi IMAGAWA Yasumasa IWASE Etsuo MASUDA 
Publication:   IEICE TRANSACTIONS on Communications
Publication Date: 1997/03/25
Vol. E80-B  No. 3 ; pp. 442-447
Type of Manuscript:  PAPER
Category: Switching and Communication Processing
Keyword: 
switchsystemfunctional blockarchitecturefirmware
 Summary | Full Text:PDF

Proposal and Performance Evaluation of a High-Speed Internetworking Device
Akira WATANABE Yuuji KOUI Shoichiro SENO Tetsuo IDEGUCHI 
Publication:   IEICE TRANSACTIONS on Communications
Publication Date: 1996/05/25
Vol. E79-B  No. 5 ; pp. 639-646
Type of Manuscript:  Special Section PAPER (Special Issue on High Speed Local Area Network)
Category: 
Keyword: 
routerperformancearchitectureinternetworkingevaluation
 Summary | Full Text:PDF

A Highly Parallel DSP Architecture for Image Recognition
Hiroyuki KAWAI Yoshitsugu INOUE Rebert STREITENBERGER Masahiko YOSHIMOTO 
Publication:   IEICE TRANSACTIONS on Fundamentals of Electronics, Communications and Computer Sciences
Publication Date: 1995/08/25
Vol. E78-A  No. 8 ; pp. 963-970
Type of Manuscript:  Special Section PAPER (Special Section on Digital Signal Processing)
Category: 
Keyword: 
image recognitionSIMDDSParchitecture
 Summary | Full Text:PDF

Functional Elements for Switching Software Based on Object-Oriented Paradigm with UPT as an Example
Fumito SATO Motoo HOSHI Yuji INOUE 
Publication:   IEICE TRANSACTIONS on Communications
Publication Date: 1992/10/25
Vol. E75-B  No. 10 ; pp. 1052-1060
Type of Manuscript:  Special Section PAPER (Special Issue on Communication Software Technologies)
Category: 
Keyword: 
object-orientedarchitecture
 Summary | Full Text:PDF