Keyword : all-digital


A Fully-Synthesizable 10.06Gbps 16.1mW Injection-Locked CDR in 28nm FDSOI
Aravind THARAYIL NARAYANAN Wei DENG Dongsheng YANG Rui WU Kenichi OKADA Akira MATSUZAWA 
Publication:   
Publication Date: 2017/03/01
Vol. E100-C  No. 3 ; pp. 259-267
Type of Manuscript:  Special Section PAPER (Special Section on Low-Power and High-Speed Chips)
Category: 
Keyword: 
fully-synthesizableall-digitalclock data recoveryinjection lockingphase-filtering
 Summary | Full Text:PDF

An All-Digital Reconfigurable Time-Domain ADC for Low-Voltage Sensor Interface in 65nm CMOS Technology
Yu HOU Takamoto WATANABE Masaya MIYAHARA Akira MATSUZAWA 
Publication:   IEICE TRANSACTIONS on Fundamentals of Electronics, Communications and Computer Sciences
Publication Date: 2015/02/01
Vol. E98-A  No. 2 ; pp. 466-475
Type of Manuscript:  Special Section PAPER (Special Section on Analog Circuit Techniques and Related Topics)
Category: 
Keyword: 
all-digitalreconfigurable resolutionTADlow-voltagesensor interface
 Summary | Full Text:PDF

All-Digital Wireless Transceiver with Sub-Sampling Demodulation and Burst-Error Correction
Sanad BUSHNAQ Makoto IKEDA Kunihiro ASADA 
Publication:   IEICE TRANSACTIONS on Fundamentals of Electronics, Communications and Computer Sciences
Publication Date: 2012/12/01
Vol. E95-A  No. 12 ; pp. 2234-2241
Type of Manuscript:  Special Section PAPER (Special Section on VLSI Design and CAD Algorithms)
Category: Circuit Design
Keyword: 
all-digitalsub-samplingerror correction
 Summary | Full Text:PDF

An All-Digital CMOS Duty Cycle Correction Circuit with a Duty-Cycle Correction Range of 15-to-85% for Multi-Phase Applications
Jang-Jin NAM Hong-June PARK 
Publication:   IEICE TRANSACTIONS on Electronics
Publication Date: 2005/04/01
Vol. E88-C  No. 4 ; pp. 773-777
Type of Manuscript:  LETTER
Category: Electronic Circuits
Keyword: 
duty cycle correctionall-digitalmulti-phase clockPLL/DLL
 Summary | Full Text:PDF