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Output Phase Optimization for AND-OR-EXOR PLAs with Decoders and Its Application to Design of Adders
Debatosh DEBNATH Tsutomu SASAO | Publication: IEICE TRANSACTIONS on Information and Systems
Publication Date: 2005/07/01
Vol. E88-D
No. 7 ;
pp. 1492-1500
Type of Manuscript:
Special Section PAPER (Special Section on Recent Advances in Circuits and Systems--Part 1)
Category: Digital Circuits and Computer Arithmetic
Keyword:
three-level network, logic minimization, adder, programmable logic, | | | Summary | Full Text:PDF | |
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A Sub-1 V Bootstrap Pass-Transistor Logic
Koji FUJII Takakuni DOUSEKI | Publication: IEICE TRANSACTIONS on Electronics
Publication Date: 2003/04/01
Vol. E86-C
No. 4 ;
pp. 604-611
Type of Manuscript:
Special Section PAPER (Special Issue on High-Performance, Low-Power System LSIs and Related Technologies)
Category: Circuit Design
Keyword:
pass-transistor logic, bootstrap, low voltage, adder, | | | Summary | Full Text:PDF | |
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A New Algorithm for the Configuration of Fast Adder Trees
Alberto PALACIOS-PAWLOVSKY | Publication: IEICE TRANSACTIONS on Fundamentals of Electronics, Communications and Computer Sciences
Publication Date: 2000/12/25
Vol. E83-A
No. 12 ;
pp. 2426-2430
Type of Manuscript:
Special Section PAPER (Special Section on VLSI Design and CAD Algorithms)
Category: VLSI Architecture
Keyword:
multiplier, adder, Wallace tree, partial product addition, Dadda tree, | | | Summary | Full Text:PDF | |
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