IEICE Trans

Keyword : accelerator

Weight Compression MAC Accelerator for Effective Inference of Deep Learning Asuka MAKI Daisuke MIYASHITA Shinichi SASAKI Kengo NAKATA Fumihiko TACHIBANA Tomoya SUZUKI Jun DEGUCHI Ryuichi FUJIMOTO
Publication: Publication Date: 2020/10/01 Vol. E103-C No. 10 ; pp. 514-523 Type of Manuscript: Special Section PAPER (Special Section on Analog Circuits and Their Application Technologies) Category: Integrated Electronics Keyword: deep learning, convolutional neural network, quantization, variable bit width, post-training, inference, accelerator, processor, FPGA,
	Summary \| Full Text:PDF

Performance Evaluation of a 3D-Stencil Library for Distributed Memory Array Accelerators Yoshikazu INAGAKI Shinya TAKAMAEDA-YAMAZAKI Jun YAO Yasuhiko NAKASHIMA
Publication: IEICE TRANSACTIONS on Information and Systems Publication Date: 2015/12/01 Vol. E98-D No. 12 ; pp. 2141-2149 Type of Manuscript: Special Section PAPER (Special Section on Parallel and Distributed Computing and Networking) Category: Architecture Keyword: CGRA, coarse grained reconfigurable architecture, accelerator, library, stencil, optimization,
	Summary \| Full Text:PDF

Design and Implement of High Performance Crypto Coprocessor Shice NI Yong DOU Kai CHEN Jie ZHOU
Publication: IEICE TRANSACTIONS on Fundamentals of Electronics, Communications and Computer Sciences Publication Date: 2014/04/01 Vol. E97-A No. 4 ; pp. 989-990 Type of Manuscript: LETTER Category: Algorithms and Data Structures Keyword: crypto coprocessor, reconfigurable crypto block, security protocol, accelerator,
	Summary \| Full Text:PDF

A Reconfigurable Data-Path Accelerator Based on Single Flux Quantum Circuits Hiroshi KATAOKA Hiroaki HONDA Farhad MEHDIPOUR Nobuyuki YOSHIKAWA Akira FUJIMAKI Hiroyuki AKAIKE Naofumi TAKAGI Kazuaki MURAKAMI
Publication: IEICE TRANSACTIONS on Electronics Publication Date: 2014/03/01 Vol. E97-C No. 3 ; pp. 141-148 Type of Manuscript: INVITED PAPER (Special Section on Leading-Edge Technology of Superconductor Large-Scale Integrated Circuits) Category: Keyword: single flux quantum, reconfigurable data-path, accelerator,
	Summary \| Full Text:PDF

Design and Implementation of a Handshake Join Architecture on FPGA Yasin OGE Takefumi MIYOSHI Hideyuki KAWASHIMA Tsutomu YOSHINAGA
Publication: IEICE TRANSACTIONS on Information and Systems Publication Date: 2012/12/01 Vol. E95-D No. 12 ; pp. 2919-2927 Type of Manuscript: Special Section PAPER (Special Section on Parallel and Distributed Computing and Networking) Category: Computer Architecture Keyword: FPGA, data stream processing, window join operator, accelerator, handshake join,
	Summary \| Full Text:PDF

Acceleration of Block Matching on a Low-Power Heterogeneous Multi-Core Processor Based on DTU Data-Transfer with Data Re-Allocation Yoshitaka HIRAMATSU Hasitha Muthumala WAIDYASOORIYA Masanori HARIYAMA Toru NOJIRI Kunio UCHIYAMA Michitaka KAMEYAMA
Publication: IEICE TRANSACTIONS on Electronics Publication Date: 2012/12/01 Vol. E95-C No. 12 ; pp. 1872-1882 Type of Manuscript: PAPER Category: Integrated Electronics Keyword: block matching, heterogeneous multi-core, dynamically reconfigurable processor, data transfer, accelerator,
	Summary \| Full Text:PDF

A Processor Accelerator for Software Decoding of Reed-Solomon Codes Kazuhito ITO Keisuke NASU
Publication: IEICE TRANSACTIONS on Fundamentals of Electronics, Communications and Computer Sciences Publication Date: 2012/05/01 Vol. E95-A No. 5 ; pp. 884-893 Type of Manuscript: PAPER Category: VLSI Design Technology and CAD Keyword: error correction code, Reed-Solomon, accelerator, decoding,
	Summary \| Full Text:PDF

A Processor Accelerator for Software Decoding of BCH Codes Kazuhito ITO
Publication: IEICE TRANSACTIONS on Fundamentals of Electronics, Communications and Computer Sciences Publication Date: 2010/07/01 Vol. E93-A No. 7 ; pp. 1329-1337 Type of Manuscript: PAPER Category: VLSI Design Technology and CAD Keyword: error correction code, BCH, accelerator, pipelining,
	Summary \| Full Text:PDF

A Configurable Common Filterbank Processor for Multi-Standard Audio Decoder Tsung-Han TSAI Chun-Nan LIU
Publication: IEICE TRANSACTIONS on Fundamentals of Electronics, Communications and Computer Sciences Publication Date: 2007/09/01 Vol. E90-A No. 9 ; pp. 1913-1923 Type of Manuscript: PAPER Category: Digital Signal Processing Keyword: audio decoder, accelerator, multi-standard, filterbank, mobile phone,
	Summary \| Full Text:PDF

Pulse Shaping for a Long-Distance Optical Synchronization System Fatih Omer ILDAY Axel WINTER Franz X. KARTNER Miltcho B. DANAILOV
Publication: IEICE TRANSACTIONS on Electronics Publication Date: 2007/02/01 Vol. E90-C No. 2 ; pp. 450-456 Type of Manuscript: INVITED PAPER (Special Section on Evolution of Microwave and Millimeter-Wave Photonics Technology) Category: Keyword: accelerator, femtosecond synchronization systems, fiber laser, ultra-short pulse propagation,
	Summary \| Full Text:PDF

A Hardware Accelerator for Java^TM Platforms on a 130-nm Embedded Processor Core Tetsuya YAMADA Naohiko IRIE Takanobu TSUNODA Takahiro IRITA Kenji KITAGAWA Ryohei YOSHIDA Keisuke TOYAMA Motoaki SATOYAMA
Publication: IEICE TRANSACTIONS on Electronics Publication Date: 2007/02/01 Vol. E90-C No. 2 ; pp. 523-530 Type of Manuscript: PAPER Category: Integrated Electronics Keyword: embedded processor, Java, accelerator, bytecode,
	Summary \| Full Text:PDF

Design of Extremum Seeking Control with Accelerator Hitoshi TAKATA Tomohiro HACHINO Ryuichiro TAMURA Kazuo KOMATSU
Publication: IEICE TRANSACTIONS on Fundamentals of Electronics, Communications and Computer Sciences Publication Date: 2005/10/01 Vol. E88-A No. 10 ; pp. 2535-2540 Type of Manuscript: Special Section PAPER (Special Section on Nonlinear Theory and its Applications) Category: Keyword: extremum seeking control, accelerator, polynomial identification, Butterworth filter, Monod model,
	Summary \| Full Text:PDF

Mincut Partitioning Acceleration Using Hardware CAD Accelerator TP5000 Masahiro SANO Shintaro SHIMOGORI Fumiyasu HIROSE
Publication: IEICE TRANSACTIONS on Fundamentals of Electronics, Communications and Computer Sciences Publication Date: 1995/12/25 Vol. E78-A No. 12 ; pp. 1785-1792 Type of Manuscript: Special Section PAPER (Special Section on VLSI Design and CAD Algorithms) Category: Keyword: mincut partitioning, SNT-FM, data pipelining, accelerator, TP5000,
	Summary \| Full Text:PDF