Keyword : accelerator


Ultra Low Power Reconfigurable Accelerator
Koichiro MASUYAMA Yu FUJITA Hayate OKUHARA Hideharu AMANO 
Publication:   - - Abstracts of (Japanese Edition)
Publication Date: 2018/05/01
Vol. J101-D  No. 5 ; pp. 729-741
Type of Manuscript:  PAPER
Category: 
Keyword: 
CGRAreconfigurableacceleratorlow powerSOTBbody bias control
 Summary | Full Text(in Japanese):PDF(2MB)

SPT: A Development Tool for Block Ciphers with Accelerators
Keisuke IWAI Masashi WATANABE Hidema TANAKA Takakazu KUROKAWA 
Publication:   - - Abstracts of (Japanese Edition)
Publication Date: 2017/06/01
Vol. J100-D  No. 6 ; pp. 627-638
Type of Manuscript:  PAPER
Category: 
Keyword: 
block cipheracceleratorparallelizing compilerCUDAHLS
 Summary | Full Text(in Japanese):PDF(2MB)

An Instruction Mapping Scheme to Add Explicit Dependability into FU Array Accelerator Execution
Suguru OOUE Jun YAO Yasuhiko NAKASHIMA 
Publication:   D - Abstracts of IEICE TRANSACTIONS on Information and Systems (Japanese Edition)
Publication Date: 2013/03/01
Vol. J96-D  No. 3 ; pp. 472-483
Type of Manuscript:  Special Section PAPER (Special Issue on Student Research)
Category: 
Keyword: 
low-poweracceleratormicroprocessorhigh-dependabilityinstruction redundancy
 Summary | Full Text(in Japanese):PDF(2.8MB)

Realizing Window Join Operator by Using FPGA
Takefumi MIYOSHI Yuta TERADA Hideyuki KAWASHIMA Tsutomu YOSHINAGA 
Publication:   B - Abstracts of IEICE TRANSACTIONS on Communications (Japanese Edition)
Publication Date: 2011/10/01
Vol. J94-B  No. 10 ; pp. 1313-1322
Type of Manuscript:  Special Section PAPER (Special Section on Internet Architecture for Smart Society)
Category: 
Keyword: 
FPGAdata stream processingwindow join operatoraccelerator
 Summary | Full Text(in Japanese):PDF(691.8KB)