Keyword : Verilog HDL


RVCoreP: An Optimized RISC-V Soft Processor of Five-Stage Pipelining
Hiromu MIYAZAKI Takuto KANAMORI Md Ashraful ISLAM Kenji KISE 
Publication:   
Publication Date: 2020/12/01
Vol. E103-D  No. 12 ; pp. 2494-2503
Type of Manuscript:  Special Section PAPER (Special Section on Parallel, Distributed, and Reconfigurable Computing, and Networking)
Category: Computer System
Keyword: 
soft processorFPGARISC-VRV32IVerilog HDLfive-stage pipelining
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