|
| Keyword : VSP
|
Low Power Design Technology for Digital LSIs
Tadayoshi ENOMOTO | Publication: IEICE TRANSACTIONS on Electronics
Publication Date: 1996/12/25
Vol. E79-C
No. 12 ;
pp. 1639-1649
Type of Manuscript:
INVITED PAPER (Special Issue on Low-Power LSI Technologies)
Category:
Keyword:
power dissipation, active power dissipation, stand-by power dissipation, low power circuit technology, LSI, CMOS LSIs, GaAs LSIs, mlulti-media LSIs, video codec LSIs, signal handling capability, throughput, clock frequency, video signal processor, VSP, DSP. H.261, MPEG2, | | | Summary | Full Text:PDF(844.4KB) | |
|
High-Throughput Technologies for Video Signal Processor (VSP) LSIs
Tadayoshi ENOMOTO | Publication: IEICE TRANSACTIONS on Electronics
Publication Date: 1996/04/25
Vol. E79-C
No. 4 ;
pp. 459-471
Type of Manuscript:
INVITED PAPER (Special Issue on Ultra-High-Speed LSIs)
Category:
Keyword:
video codec LSIs, video signal processor, VSP, DSP, video data encoding, decoding, H.261, MPEG2, power dissipation, throughtput, | | | Summary | Full Text:PDF(1.2MB) | |
|
A PLL-Based Programmable Clock Generator with 50-to 350-MHz Oscillating Range for Video Signal Processors
Junichi GOTO Masakazu YAMASHINA Toshiaki INOUE Benjamin S. SHIH Youichi KOSEKI Tadahiko HORIUCHI Nobuhisa HAMATAKE Kouichi KUMAGAI Tadayoshi ENOMOTO Hachiro YAMADA | Publication: IEICE TRANSACTIONS on Electronics
Publication Date: 1994/12/25
Vol. E77-C
No. 12 ;
pp. 1951-1956
Type of Manuscript:
Special Section PAPER (Special Issue on Multimedia, Analog and Processing LSIs)
Category: Processor Interfaces
Keyword:
electronic circuits, clock generator, PLL, frequency multiplication, VCO, VCO gain, jitter, pull-in range, CMOS, VSP, | | | Summary | Full Text:PDF(691.7KB) | |
|
|
